upsilon/firmware/rtl
Peter McGoron 0a9125355f disable test clock by default 2023-05-11 15:31:52 -04:00
..
base disable test clock by default 2023-05-11 15:31:52 -04:00
control_loop update boothmul properly; add clean to make; hardware notes 2023-05-11 14:37:32 -04:00
raster arty.xdc for synth test 2023-03-20 13:58:35 -04:00
spi reset pins and test clock 2023-05-10 14:35:57 -04:00
waveform reset pins and test clock 2023-05-10 14:35:57 -04:00
Makefile pass yosys 2023-03-15 17:08:55 -04:00
common.makefile reset pins and test clock 2023-05-10 14:35:57 -04:00
testbench.hpp simulate waveform.v 2023-03-15 06:24:28 +00:00
util.hpp test and simulate spi_switch 2023-03-14 15:42:41 +00:00