Peter McGoron 223d2f98c6 add pre_finalize() to PreemptiveInterface ... CSR scans run *before* do_finalize() is called. This is a silent failure: The signals get generated but the CSR is not in the csr.json file or the generated verilog. pre_finalize() is a function that must be called when all masters are added to the module. This will generate the CSR before finalization, (hopefully) ensuring that the CSR is added to the CSR bus. I need to figure out a way to excise manual use of the CSR bus from the design. Future options may include having a PreemptiveInterface control module sitting in front of the PreemptiveInterfaces that exposes the control lines as a Wishbone register.		2024-03-07 15:59:08 +00:00
..
rtl	waveform: finish basic tests	2024-03-03 23:05:29 +00:00
A7-constraints.xdc	firmware is a form of software; gateware is the equivalent for FGPAs	2023-06-14 15:31:49 -04:00
Makefile	waveform: write and start simulation	2024-03-03 22:35:19 +00:00
config.py.def	Get PicoRV32 to execute code	2024-02-25 18:58:34 +00:00
extio.py	Integrate Waveform into SoC; Rework PreemptiveInterface	2024-03-06 21:17:51 +00:00
region.py	Documentation and register location generation	2024-02-28 13:28:06 +00:00
soc.py	add pre_finalize() to PreemptiveInterface	2024-03-07 15:59:08 +00:00
swic.py	add pre_finalize() to PreemptiveInterface	2024-03-07 15:59:08 +00:00
util.py	Documentation, fix parameter passing	2024-02-26 06:02:48 +00:00