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Free and open source SoC for Scanning Probe Microscopy
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Peter McGoron 223d2f98c6 add pre_finalize() to PreemptiveInterface 
CSR scans run *before* do_finalize() is called. This is a silent
failure: The signals get generated but the CSR is not in the csr.json
file or the generated verilog.

pre_finalize() is a function that must be called when all masters are
added to the module. This will generate the CSR before finalization,
(hopefully) ensuring that the CSR is added to the CSR bus.

I need to figure out a way to excise manual use of the CSR bus from the
design. Future options may include having a PreemptiveInterface
control module sitting in front of the PreemptiveInterfaces that exposes
the control lines as a Wishbone register.
 		2024-03-07 15:59:08 +00:00
boot sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
build waveform: finish basic tests 2024-03-03 23:05:29 +00:00
buildroot Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:59:34 -04:00
client Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:59:34 -04:00
doc Integrate Waveform into SoC; Rework PreemptiveInterface 2024-03-06 21:17:51 +00:00
gateware add pre_finalize() to PreemptiveInterface 2024-03-07 15:59:08 +00:00
linux z output reading 2023-06-27 17:50:55 -04:00
opensbi/litex/vexriscv refactor control loop interface 2023-06-28 17:38:41 -04:00
swic Documentation and register location generation 2024-02-28 13:28:06 +00:00
.gitignore Get PicoRV32 to execute code 2024-02-25 18:58:34 +00:00
README.md update README.md 2024-02-04 17:00:35 +00:00

README.md

upsilon

Upsilon is a 100% free and open source STM/AFM controller for FPGAs running Linux. Read doc/copying/README.md for license information.

Quickstart

Read doc/docker.md to set up the Docker build environment.

Project Organization

  • boot: This folder is the central place for all built files. This includes the kernel image, rootfs, gateware, etc. This directory also includes everything the TFTP server has to access.
  • build: Docker build environment.
  • buildroot: Buildroot configuration files.
  • doc: Documentation.
  • doc/copying: Licenses.
  • gateware: FPGA source.
  • gateware/rtl: Verilog sources.
  • gateware/rtl/spi: SPI code (from another repo)
  • linux: Software that runs on the controller.
  • opensbi: OpenSBI configuration files and source fragments.
  • swic: Code that runs on the PicoRV32 soft core.