upsilon/gateware/rtl
Peter McGoron 9f76e03028 Minor SPI fixes and Interconnect fix
The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
2024-02-03 00:33:52 +00:00
..
base refactor compiles 2023-06-28 18:49:26 -04:00
bram bram: integrate into SoC using Wishbone bus, and note alignment 2024-01-21 04:38:34 +00:00
control_loop Removed reference to non-existent file 2023-08-07 23:49:18 -04:00
picorv32 picorv32 integration, take 1 2024-02-02 15:24:18 -05:00
raster make lawyers happy 2023-06-15 12:24:35 -04:00
spi Minor SPI fixes and Interconnect fix 2024-02-03 00:33:52 +00:00
waveform make lawyers happy 2023-06-15 12:24:35 -04:00
Makefile fix Makefile bram codegen 2024-01-20 20:43:12 +00:00
common.makefile make lawyers happy 2023-06-15 12:24:35 -04:00
testbench.hpp make lawyers happy 2023-06-15 12:24:35 -04:00
util.hpp make lawyers happy 2023-06-15 12:24:35 -04:00