Peter McGoron 487d638aa5 Integrate Waveform into SoC; Rework PreemptiveInterface ... New master buses can be added to PreemptiveInterface throughout the code, simplifying the main SoC code. This removes the requirement that the amount of masters to the interface needs to be known at instantiation time.		2024-03-06 21:17:51 +00:00
..
rtl	waveform: finish basic tests	2024-03-03 23:05:29 +00:00
A7-constraints.xdc	firmware is a form of software; gateware is the equivalent for FGPAs	2023-06-14 15:31:49 -04:00
Makefile	waveform: write and start simulation	2024-03-03 22:35:19 +00:00
config.py.def	Get PicoRV32 to execute code	2024-02-25 18:58:34 +00:00
extio.py	Integrate Waveform into SoC; Rework PreemptiveInterface	2024-03-06 21:17:51 +00:00
region.py	Documentation and register location generation	2024-02-28 13:28:06 +00:00
soc.py	Integrate Waveform into SoC; Rework PreemptiveInterface	2024-03-06 21:17:51 +00:00
swic.py	Integrate Waveform into SoC; Rework PreemptiveInterface	2024-03-06 21:17:51 +00:00
util.py	Documentation, fix parameter passing	2024-02-26 06:02:48 +00:00