56 lines
1.1 KiB
C++
56 lines
1.1 KiB
C++
/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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#pragma once
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#include <verilated.h>
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#include "util.hpp"
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/* https://zipcpu.com/blog/2017/06/21/looking-at-verilator.html */
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template <class TOP> class TB {
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int tick_count;
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int bailout;
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public:
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TOP mod;
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TB(int _bailout = 0) : mod(), bailout(_bailout) {
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mod.clk = 0;
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tick_count = 0;
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}
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virtual ~TB() {
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mod.final();
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}
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/* This function is called at the positive edge of ever clock
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* cycle.
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*
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* It's intended use is for glue code, like a bus handler.
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*
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* The bulk of the simulation code (driving external inputs into the
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* simulated module and observing results) should be done outside of
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* this function.
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*/
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virtual void posedge() {}
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void run_clock() {
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mod.clk = !mod.clk;
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mod.eval();
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Verilated::timeInc(1);
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posedge();
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mod.clk = !mod.clk;
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mod.eval();
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Verilated::timeInc(1);
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tick_count++;
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if (bailout > 0 && tick_count >= bailout) {
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exit(1);
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} if (Verilated::gotError()) {
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exit(1);
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}
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}
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};
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