diff options
| author |  Peter McGoron
| 2023-02-11 21:24:48 +0000 |
|---|---|---|
| committer | Peter McGoron
| 2023-02-11 21:24:48 +0000 |
| commit | b425e26ea3ff2df3f6b98b475ae870900efaf2e6 (patch) | |
| tree | d134435547ee287f23b237b4be0c14bd353d87a7 /asm | |
| parent | rename idiv to sdiv (diff) | |
jump tests
Diffstat (limited to 'asm')
| -rw-r--r-- | asm/creole.py | 13 | ||||
| -rw-r--r-- | asm/ffi.py | 4 | ||||
| -rw-r--r-- | asm/test.py | 16 |
3 files changed, 30 insertions, 3 deletions
diff --git a/asm/creole.py b/asm/creole.py index 1d98051..4cb4b8c 100644 --- a/asm/creole.py +++ b/asm/creole.py @@ -92,9 +92,14 @@ class Instruction(Enum): MUL = 4, ArgType.REG, ArgType.VAL, ArgType.VAL DIV = 5, ArgType.REG, ArgType.VAL, ArgType.VAL SDIV = 6, ArgType.REG, ArgType.VAL, ArgType.VAL - JL = 7, ArgType.LAB, ArgType.VAL, ArgType.VAL + SYS = 7, ArgType.VAL CLB = 8, ArgType.LAB - SYS = 9, ArgType.VAL + JL = 9, ArgType.LAB, ArgType.VAL, ArgType.VAL + JLE = 10, ArgType.LAB, ArgType.VAL, ArgType.VAL + JG = 11, ArgType.LAB, ArgType.VAL, ArgType.VAL + JGE = 12, ArgType.LAB, ArgType.VAL, ArgType.VAL + JE = 13, ArgType.LAB, ArgType.VAL, ArgType.VAL + JNE = 13, ArgType.LAB, ArgType.VAL, ArgType.VAL def __init__(self, opcode, *args): if opcode > 0x7F or opcode < 0: @@ -214,6 +219,10 @@ class Program: args_w_type = ins.typecheck(line[1:]) self.asm_push_line(ins.opcode, args_w_type) + def parse_lines(self, lines): + for l in lines: + self.parse_asm_line(l) + def __call__(self): b = bytes() for line in self.asm: @@ -120,13 +120,15 @@ class Environment: def syscall(self, sc): raise InvalidSyscallError(sc) - def __call__(self): + def __call__(self, debug=False): sc = c_size_t() ret = RunRet.CONTINUE while not ret.is_halt(): ret = RunRet(dll.creole_step(byref(self.cenv), byref(sc))) if ret == RunRet.SYSCALL: self.syscall(sc) + if debug: + print(self.cenv.reg[0]) return ret class CParseLineException(Exception): diff --git a/asm/test.py b/asm/test.py index 4b6471c..00e9e5e 100644 --- a/asm/test.py +++ b/asm/test.py @@ -309,6 +309,22 @@ class DivTest(unittest.TestCase): self.assertEqual(cm.exception.i, 2) self.assertEqual(cm.exception.opcode, 5) +class LabelTest(unittest.TestCase): + def test_simple_loop(self): + p = Program() + p.parse_lines([ + "add r0 10 0", + "add r1 20 0", + "CLB l0", + "add r0 r0 -1", + "add r1 r1 1", + "jg l0 r0 0" + ]) + ex = ffi.Environment(p()) + self.assertEqual(ex(), ffi.RunRet.STOP) + self.assertEqual(ex.getreg(0), 0) + self.assertEqual(ex.getreg(1), 30) + class ProgramTest(unittest.TestCase): def test_exec_simple_reg(self): p = Program() |