successfully test mode01, add Makefile

This commit is contained in:
Peter McGoron 2022-07-21 03:01:58 -04:00
parent bc66e5c658
commit d8b011110a
6 changed files with 54 additions and 10 deletions

7
tests/Makefile Normal file
View File

@ -0,0 +1,7 @@
all:
for i in 00 01; do \
make -f run_mode.makefile MODE="$$i"; \
done
clean:
rm -rf obj_dir

3
tests/mode01.cpp Normal file
View File

@ -0,0 +1,3 @@
#include "Vmode01.h"
using TopModule = Vmode01;
#include "write_read.cpp"

34
tests/mode01.v Normal file
View File

@ -0,0 +1,34 @@
/* (c) Peter McGoron 2022
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v.2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
module mode01 (
input clk,
input [23:0] data_ctrl,
input activate,
input ss,
input rdy,
output master_finished
);
spi_write_read
#(
.POLARITY(0),
.PHASE(1)
) base (
.clk(clk),
.data_ctrl(data_ctrl),
.activate(activate),
.master_finished(master_finished),
.ss(ss),
.rdy(rdy)
);
initial begin
$dumpfile("mode01.vcd");
$dumpvars();
end
endmodule

View File

@ -1,5 +0,0 @@
#!/bin/sh
for i in 00; do
make -f run_mode.makefile MODE="$i"
done

View File

@ -12,7 +12,7 @@ WAVEFILE=${TESTBENCH_BASE}.vcd
FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH} FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH}
all: obj_dir/V${TESTBENCH_BASE} all: obj_dir/V${TESTBENCH_BASE}
./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE} ./obj_dir/V${TESTBENCH_BASE}
obj_dir/V${TESTBENCH_BASE}.mk: ${FILES} obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
verilator -CFLAGS -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE} verilator -CFLAGS -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}

View File

@ -27,8 +27,11 @@ reg [23:0] from_slave_data;
reg slave_finished; reg slave_finished;
reg slave_error; reg slave_error;
spi_master master spi_master
( #(
.POLARITY(POLARITY),
.PHASE(PHASE)
) master (
.clk(clk), .clk(clk),
.to_slave(data_ctrl), .to_slave(data_ctrl),
.from_slave(from_slave_data), .from_slave(from_slave_data),
@ -42,8 +45,10 @@ spi_master master
reg [23:0] data_from_master; reg [23:0] data_from_master;
reg [23:0] data_to_master = 24'b111011011100010101010101; reg [23:0] data_to_master = 24'b111011011100010101010101;
spi_slave slave spi_slave #(
( .POLARITY(POLARITY),
.PHASE(PHASE)
) slave (
.clk(clk), .clk(clk),
.sck(sck), .sck(sck),
.ss_L(ss_L), .ss_L(ss_L),