108 lines
1.6 KiB
Verilog
108 lines
1.6 KiB
Verilog
/* (c) Peter McGoron 2022-2024 v0.4
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*
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* This code is disjunctively dual-licensed under the MPL v2.0, or the
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* CERN-OHL-W v2.
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*/
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module simtop
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#(
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parameter ENABLE_MOSI = 1,
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parameter ENABLE_MISO = 1,
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parameter POLARITY = 0,
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parameter PHASE = 0,
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parameter WID = 24,
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parameter WID_LEN = 5
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) (
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input clk,
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input rst_L,
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input [WID-1:0] master_to_slave,
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output [WID-1:0] from_master,
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input [WID-1:0] slave_to_master,
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output [WID-1:0] from_slave,
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input activate,
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`ifndef SPI_MASTER_SS
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input ss,
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`endif
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input rdy,
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output master_finished,
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output ready_to_arm,
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output err
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);
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wire miso;
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wire mosi;
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wire sck;
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wire ss_L;
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`ifndef SPI_MASTER_SS
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assign ss_L = !ss;
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`endif
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wire slave_finished;
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wire slave_error;
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`SPI_MASTER_TYPE
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#(
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`ifdef SPI_MASTER_SS
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.SS_WAIT(5),
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.SS_WAIT_TIMER_LEN(3),
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`endif
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.ENABLE_MOSI(ENABLE_MOSI),
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.ENABLE_MISO(ENABLE_MISO),
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.CYCLE_HALF_WAIT(5),
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.TIMER_LEN(3),
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.POLARITY(POLARITY),
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.PHASE(PHASE),
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.WID(WID),
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.WID_LEN(WID_LEN)
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) master (
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.clk(clk),
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.rst_L(rst_L),
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.to_slave(master_to_slave),
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.mosi(mosi),
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.from_slave(from_slave),
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.miso(miso),
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`ifdef SPI_MASTER_SS
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.ss_L(ss_L),
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`endif
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.sck_wire(sck),
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.finished(master_finished),
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.ready_to_arm(ready_to_arm),
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.arm(activate)
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);
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spi_slave #(
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.ENABLE_MOSI(ENABLE_MOSI),
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.ENABLE_MISO(ENABLE_MISO),
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.POLARITY(POLARITY),
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.PHASE(PHASE),
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.WID(WID),
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.WID_LEN(WID_LEN)
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) slave (
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.clk(clk),
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.rst_L(rst_L),
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.sck(sck),
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.ss_L(ss_L),
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.from_master(from_master),
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.mosi(mosi),
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.to_master(slave_to_master),
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.miso(miso),
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.finished(slave_finished),
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.rdy(rdy),
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.err(err)
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);
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`ifdef SIMULATION
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initial begin
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$dumpfile(`VCDFILE);
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$dumpvars;
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end
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`endif
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endmodule
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