VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/Makefile



VERILOG = ../../../Murax.v toplevel.v

generate :
	(cd ../../..; sbt "run-main vexriscv.demo.Murax")

../../../Murax.v :
	(cd ../../..; sbt "run-main vexriscv.demo.Murax")

../../../Murax.v*.bin:

bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin
	mkdir -p bin
	rm -f Murax.v*.bin
	cp ../../../Murax.v*.bin . | true
	yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG}

bin/toplevel.asc : toplevel.pcf bin/toplevel.blif
	arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc

bin/toplevel.bin : bin/toplevel.asc
	icepack bin/toplevel.asc bin/toplevel.bin

compile : bin/toplevel.bin

time: bin/toplevel.bin
	icetime -tmd hx8k bin/toplevel.asc

prog : bin/toplevel.bin
	iceprog -S bin/toplevel.bin

sudo-prog : bin/toplevel.bin
	sudo iceprog -S bin/toplevel.bin

clean :
	rm -rf bin
	rm -f Murax.v*.bin
Add Murax scripts 2017-07-29 16:43:43 -04:00

Clean script folder 2017-12-29 07:18:14 -05:00			`VERILOG = ../../../Murax.v toplevel.v`
Add Murax scripts 2017-07-29 16:43:43 -04:00
scripts/murax better makefile, add pullup on jtag interface 2017-08-03 17:22:57 -04:00			`generate :`
Clean script folder 2017-12-29 07:18:14 -05:00			`(cd ../../..; sbt "run-main vexriscv.demo.Murax")`
Add Murax scripts 2017-07-29 16:43:43 -04:00
Clean script folder 2017-12-29 07:18:14 -05:00			`../../../Murax.v :`
			`(cd ../../..; sbt "run-main vexriscv.demo.Murax")`
scripts/murax better makefile, add pullup on jtag interface 2017-08-03 17:22:57 -04:00
Fix Murax script flow (without rom file) 2018-01-21 09:39:10 -05:00			`../../../Murax.v*.bin:`

SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 12:29:33 -05:00			`bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin`
Add Murax scripts 2017-07-29 16:43:43 -04:00			`mkdir -p bin`
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 12:29:33 -05:00			`rm -f Murax.v*.bin`
			`cp ../../../Murax.v*.bin . \| true`
Add Murax scripts 2017-07-29 16:43:43 -04:00			`yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG}`

scripts/murax better makefile, add pullup on jtag interface 2017-08-03 17:22:57 -04:00			`bin/toplevel.asc : toplevel.pcf bin/toplevel.blif`
			`arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc`
Add Murax scripts 2017-07-29 16:43:43 -04:00
scripts/murax better makefile, add pullup on jtag interface 2017-08-03 17:22:57 -04:00			`bin/toplevel.bin : bin/toplevel.asc`
			`icepack bin/toplevel.asc bin/toplevel.bin`
Add Murax scripts 2017-07-29 16:43:43 -04:00
			`compile : bin/toplevel.bin`

			`time: bin/toplevel.bin`
			`icetime -tmd hx8k bin/toplevel.asc`

			`prog : bin/toplevel.bin`
Adding sudo-prog to hx8k_breakout_board example. 2018-07-20 21:30:26 -04:00			`iceprog -S bin/toplevel.bin`

			`sudo-prog : bin/toplevel.bin`
Add Murax scripts 2017-07-29 16:43:43 -04:00			`sudo iceprog -S bin/toplevel.bin`

Update murax readme 2017-07-31 07:57:34 -04:00			`clean :`
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 12:29:33 -05:00			`rm -rf bin`
Adding sudo-prog to hx8k_breakout_board example. 2018-07-20 21:30:26 -04:00			`rm -f Murax.v*.bin`