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VexRiscv
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This commit is contained in:
Dolu1990 2021-03-04 16:06:18 +01:00
parent caf1bde49b
commit 0530d22a1d
2 changed files with 3 additions and 1 deletions
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3
src/main/scala/vexriscv/plugin/Plugin.scala
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@ -10,7 +10,10 @@ trait Plugin[T <: Pipeline] extends Nameable{
var pipeline : T = null.asInstanceOf[T] var pipeline : T = null.asInstanceOf[T]
setName(this.getClass.getSimpleName.replace("$","")) setName(this.getClass.getSimpleName.replace("$",""))
// Used to setup things with other plugins
def setup(pipeline: T) : Unit = {} def setup(pipeline: T) : Unit = {}
//Used to flush out the required hardware (called after setup)
def build(pipeline: T) : Unit def build(pipeline: T) : Unit
implicit class implicitsStage(stage: Stage){ implicit class implicitsStage(stage: Stage){

1
src/test/scala/vexriscv/ip/fpu/FpuTest.scala
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@ -68,7 +68,6 @@ class FpuTest extends FunSuite{
dut.clockDomain.forkSimSpeedPrinter(5.0) dut.clockDomain.forkSimSpeedPrinter(5.0)
class TestCase(op : String){ class TestCase(op : String){
def build(arg : String) = new ProcessStream(s"testfloat_gen $arg -tininessafter -forever -$op"){ def build(arg : String) = new ProcessStream(s"testfloat_gen $arg -tininessafter -forever -$op"){
def f32_f32_f32 ={ def f32_f32_f32 ={