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improve debugPlugin step logic

This commit is contained in:
Dolu1990 2020-03-03 15:59:30 +01:00
parent fd37962a58
commit 12463e40a4
1 changed files with 5 additions and 2 deletions
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7
src/main/scala/vexriscv/plugin/DebugPlugin.scala
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@ -213,11 +213,14 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
iBusFetcher.haltIt() iBusFetcher.haltIt()
} }
when(stepIt && iBusFetcher.incoming()) { when(stepIt) {
iBusFetcher.haltIt() //Assume nothing will stop the CPU in the decode stage
when(decode.arbitration.isValid) { when(decode.arbitration.isValid) {
haltIt := True haltIt := True
} }
when(execute.arbitration.isValid) {
decode.arbitration.flushNext := True
}
} }
//Avoid having two C instruction executed in a single step //Avoid having two C instruction executed in a single step