improve debugPlugin step logic

src/main/scala/vexriscv/plugin/DebugPlugin.scala

@@ -213,11 +213,14 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
         iBusFetcher.haltIt()
       }
 
-      when(stepIt && iBusFetcher.incoming()) {
-        iBusFetcher.haltIt()
+      when(stepIt) {
+        //Assume nothing will stop the CPU in the decode stage
         when(decode.arbitration.isValid) {
           haltIt := True
         }
+        when(execute.arbitration.isValid) {
+          decode.arbitration.flushNext := True
+        }
       }
 
       //Avoid having two C instruction executed in a single step