Better readme about custum instruction testing

README.md

@@ -438,8 +438,11 @@ class SimdAddPlugin extends Plugin[VexRiscv]{
     import pipeline._
     import pipeline.config._
 
+    //Add a new scope on the execute stage (used to give a name to signals)
+    execute plug new Area {
       //Define some signals used internally to the plugin
-    val rs1 = execute.input(RS1).asUInt //32 bits UInt value of the regfile[RS1]
+      val rs1 = execute.input(RS1).asUInt
+      //32 bits UInt value of the regfile[RS1]
       val rs2 = execute.input(RS2).asUInt
       val rd = UInt(32 bits)
 
@@ -455,6 +458,7 @@ class SimdAddPlugin extends Plugin[VexRiscv]{
       }
     }
   }
+}
 ```
 
 Then if you want to add this plugin to a given CPU, you just need to add it in its parameterized plugin list.
@@ -469,3 +473,16 @@ This example is a very simple one, but each plugin can really have access to the
 - override published signals values
 - Provide an alternative implementation
 - ...
+
+As a demonstrator, this SimdAddPlugin was integrated in the src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala CPU configuration and is self tested by the src/test/cpp/custom/simd_add application by running the following commands :
+
+```sh
+cd src/test/cpp/regression/
+
+# Optionally add TRACE=yes if you want to get the VCD waveform from the simulation.
+# Also you have to know that by default, the testbench introduce instruction/data bus stall.
+# Note the CUSTOM_SIMD_ADD flag is set to yes.
+make clean run IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no DHRYSTONE=no REDO=2 CUSTOM_SIMD_ADD=yes
+```
+
+To retrieve the plugin related signals in the wave, just filter with `simd`.

src/main/scala/vexriscv/demo/CustomInstruction.scala

@@ -53,6 +53,8 @@ class SimdAddPlugin extends Plugin[VexRiscv]{
     import pipeline._
     import pipeline.config._
 
+    //Add a new scope on the execute stage (used to give a name to signals)
+    execute plug new Area {
       //Define some signals used internally to the plugin
       val rs1 = execute.input(RS1).asUInt //32 bits UInt value of the regfile[RS1]
       val rs2 = execute.input(RS2).asUInt
@@ -70,3 +72,4 @@ class SimdAddPlugin extends Plugin[VexRiscv]{
       }
     }
   }
+}

src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala

@@ -36,12 +36,12 @@ object GenCustomSimdAdd extends App{
           separatedAddSub = false,
           executeInsertion = false
         ),
-        new LightShifterPlugin,
+        new FullBarrielShifterPlugin,
         new HazardSimplePlugin(
-          bypassExecute           = false,
-          bypassMemory            = false,
-          bypassWriteBack         = false,
-          bypassWriteBackBuffer   = false,
+          bypassExecute           = true,
+          bypassMemory            = true,
+          bypassWriteBack         = true,
+          bypassWriteBackBuffer   = true,
           pessimisticUseSrc       = false,
           pessimisticWriteRegFile = false,
           pessimisticAddressMatch = false