privileged debug now access data cache with caching enable
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486d17d245
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@ -801,7 +801,6 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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case p : PredictionInterface => p.inDebugNoFetch()
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case _ =>
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}
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if(pipeline.things.contains(DEBUG_BYPASS_CACHE)) pipeline(DEBUG_BYPASS_CACHE) := True
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}
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val wakeService = serviceElse(classOf[IWake], null)
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@ -864,7 +863,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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val tdata1 = new Area{
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val read = B(0, 32 bits)
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val tpe = Reg(UInt(4 bits)) init(2)
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val tpe = U(2, 4 bits)
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val dmode = Reg(Bool()) init(False)
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val execute = RegInit(False)
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@ -877,8 +876,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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default -> False
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)
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csrrw(CSR.TDATA1, read, 2 -> execute , 3 -> u, 4-> s, 6 -> m, 32 - 4 -> tpe, 32 - 5 -> dmode, 12 -> action)
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csrrw(CSR.TDATA1, read, 2 -> execute , 3 -> u, 4-> s, 6 -> m, 32 - 5 -> dmode, 12 -> action)
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csrr(CSR.TDATA1, read, 32 - 4 -> tpe)
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//TODO action sizelo timing select sizehi maskmax
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}
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