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CsrOpensbi now add rvc to misa

This commit is contained in:
Dolu1990 2022-10-21 18:58:13 +02:00
parent 662943522f
commit 486d17d245
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -201,8 +201,9 @@ object VexRiscvSmpClusterGen {
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
assert(!(withDouble && !withFloat))
val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "s" else ""}")
val csrConfig = if(withSupervisor){
CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug)
CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug)
} else {
CsrPluginConfig(
catchIllegalAccess = true,
@ -210,7 +211,7 @@ object VexRiscvSmpClusterGen {
marchid = null,
mimpid = null,
mhartid = hartId,
misaExtensionsInit = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s"),
misaExtensionsInit = misa,
misaAccess = if(forceMisa) CsrAccess.WRITE_ONLY else CsrAccess.NONE,
mtvecAccess = CsrAccess.READ_WRITE,
mtvecInit = null,