Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #182 from rdolbeau/extra_config 

Make the [ID]TLB size configurable from Litex
This commit is contained in:
Dolu1990 2021-05-12 13:54:27 +02:00 committed by GitHub
parent fe739b907a 1bd33a369e
commit 1c3b9e93a2
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -184,7 +184,9 @@ object VexRiscvSmpClusterGen {
decoderIsolationBench : Boolean = false,
decoderStupid : Boolean = false,
regfileRead : RegFileReadKind = plugin.ASYNC,
rvc : Boolean = false
rvc : Boolean = false,
iTlbSize : Int = 4,
dTlbSize : Int = 4
) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
@ -221,7 +223,7 @@ object VexRiscvSmpClusterGen {
reducedBankWidth = true
),
memoryTranslatorPortConfig = MmuPortConfig(
portTlbSize = 4,
portTlbSize = iTlbSize,
latency = 1,
earlyRequireMmuLockup = true,
earlyCacheHits = true
@ -249,7 +251,7 @@ object VexRiscvSmpClusterGen {
withWriteAggregation = dBusWidth > 32
),
memoryTranslatorPortConfig = MmuPortConfig(
portTlbSize = 4,
portTlbSize = dTlbSize,
latency = 1,
earlyRequireMmuLockup = true,
earlyCacheHits = true

8
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
View File

@ -118,6 +118,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
var rvc = false
var netlistDirectory = "."
var netlistName = "VexRiscvLitexSmpCluster"
var iTlbSize = 4
var dTlbSize = 4
assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
help("help").text("prints this usage text")
opt[Unit]("coherent-dma") action { (v, c) => coherentDma = true }
@ -137,6 +139,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
opt[String]("fpu" ) action { (v, c) => fpu = v.toBoolean }
opt[String]("cpu-per-fpu") action { (v, c) => cpuPerFpu = v.toInt }
opt[String]("rvc") action { (v, c) => rvc = v.toBoolean }
opt[String]("itlb-size") action { (v, c) => iTlbSize = v.toInt }
opt[String]("dtlb-size") action { (v, c) => dTlbSize = v.toInt }
}.parse(args))
val coherency = coherentDma || cpuCount > 1
@ -161,7 +165,9 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
externalFpu = fpu,
loadStoreWidth = if(fpu) 64 else 32,
rvc = rvc,
injectorStage = rvc
injectorStage = rvc,
iTlbSize = iTlbSize,
dTlbSize = dTlbSize
)
if(aesInstruction) c.add(new AesPlugin)
c