Fix mprv and add it into the softare model
This commit is contained in:
Dolu1990
parent
1ec11dc03d
commit
1c3fd5c38b
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@ -12,19 +12,19 @@ Disassembly of section .init:
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#endif*/
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la sp, _sp
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80000000: 00001117 auipc sp,0x1
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80000004: cb010113 addi sp,sp,-848 # 80000cb0 <_sp>
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80000004: dd810113 addi sp,sp,-552 # 80000dd8 <_sp>
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/* Load data section */
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la a0, _data_lma
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80000008: 00000517 auipc a0,0x0
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8000000c: 43450513 addi a0,a0,1076 # 8000043c <__init_array_end>
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8000000c: 55c50513 addi a0,a0,1372 # 80000564 <__init_array_end>
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la a1, _data
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80000010: 00000597 auipc a1,0x0
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80000014: 42c58593 addi a1,a1,1068 # 8000043c <__init_array_end>
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80000014: 55458593 addi a1,a1,1364 # 80000564 <__init_array_end>
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la a2, _edata
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80000018: 00000617 auipc a2,0x0
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8000001c: 49860613 addi a2,a2,1176 # 800004b0 <__bss_start>
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8000001c: 5c060613 addi a2,a2,1472 # 800005d8 <__bss_start>
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bgeu a1, a2, 2f
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80000020: 00c5fc63 bleu a2,a1,80000038 <_start+0x38>
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1:
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@ -43,10 +43,10 @@ Disassembly of section .init:
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/* Clear bss section */
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la a0, __bss_start
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80000038: 00000517 auipc a0,0x0
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8000003c: 47850513 addi a0,a0,1144 # 800004b0 <__bss_start>
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8000003c: 5a050513 addi a0,a0,1440 # 800005d8 <__bss_start>
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la a1, _end
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80000040: 00000597 auipc a1,0x0
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80000044: 47058593 addi a1,a1,1136 # 800004b0 <__bss_start>
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80000044: 59858593 addi a1,a1,1432 # 800005d8 <__bss_start>
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bgeu a0, a1, 2f
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80000048: 00b57863 bleu a1,a0,80000058 <_start+0x58>
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1:
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@ -59,7 +59,7 @@ Disassembly of section .init:
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2:
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call __libc_init_array
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80000058: 34c000ef jal ra,800003a4 <__libc_init_array>
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80000058: 474000ef jal ra,800004cc <__libc_init_array>
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call init
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8000005c: 128000ef jal ra,80000184 <init>
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la ra, done
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@ -156,7 +156,7 @@ trapEntry:
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sw x31, 31*4(sp)
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800000f8: 07f12e23 sw t6,124(sp)
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call trap
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800000fc: 134000ef jal ra,80000230 <trap>
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800000fc: 1e8000ef jal ra,800002e4 <trap>
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lw x0, 0*4(sp)
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80000100: 00012003 lw zero,0(sp)
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lw x1, 1*4(sp)
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@ -227,20 +227,18 @@ trapEntry:
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Disassembly of section .text:
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80000184 <init>:
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extern const unsigned int _sp;
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extern void trapEntry();
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extern void emulationTrap();
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void init() {
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unsigned int sp = (unsigned int) (&_sp);
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csr_write(mtvec, trapEntry);
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80000184: 800007b7 lui a5,0x80000
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80000188: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff3cc>
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80000188: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff2a4>
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8000018c: 30579073 csrw mtvec,a5
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unsigned int sp = (unsigned int) (&_sp);
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80000190: 800017b7 lui a5,0x80001
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80000194: cb078793 addi a5,a5,-848 # 80000cb0 <_sp+0x0>
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csr_write(mscratch, sp -32*4);
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80000190: 800017b7 lui a5,0x80001
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80000194: dd878793 addi a5,a5,-552 # 80000dd8 <_sp+0x0>
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80000198: f8078793 addi a5,a5,-128
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8000019c: 34079073 csrw mscratch,a5
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csr_write(mstatus, 0x0800);
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@ -263,10 +261,10 @@ int readRegister(int id){
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return ((int*) sp)[id-32];
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800001c0: 00251513 slli a0,a0,0x2
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800001c4: 800017b7 lui a5,0x80001
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800001c8: cb078793 addi a5,a5,-848 # 80000cb0 <_sp+0x0>
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800001c8: dd878793 addi a5,a5,-552 # 80000dd8 <_sp+0x0>
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800001cc: 00f50533 add a0,a0,a5
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}
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800001d0: f8052503 lw a0,-128(a0) # 80ffff80 <_sp+0xfff2d0>
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800001d0: f8052503 lw a0,-128(a0) # 80ffff80 <_sp+0xfff1a8>
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800001d4: 00008067 ret
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800001d8 <writeRegister>:
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@ -275,7 +273,7 @@ void writeRegister(int id, int value){
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((int*) sp)[id-32] = value;
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800001d8: 00251513 slli a0,a0,0x2
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800001dc: 800017b7 lui a5,0x80001
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800001e0: cb078793 addi a5,a5,-848 # 80000cb0 <_sp+0x0>
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800001e0: dd878793 addi a5,a5,-552 # 80000dd8 <_sp+0x0>
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800001e4: 00f50533 add a0,a0,a5
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800001e8: f8b52023 sw a1,-128(a0)
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}
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@ -286,7 +284,7 @@ void writeRegister(int id, int value){
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void stopSim(){
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*((volatile int*) SIM_STOP) = 0;
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800001f0: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7ffff34c>
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800001f0: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7ffff224>
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}
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800001f4: 00008067 ret
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@ -294,7 +292,7 @@ void stopSim(){
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void putC(char c){
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*((volatile int*) PUTC) = c;
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800001f8: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7ffff348>
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800001f8: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7ffff220>
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}
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800001fc: 00008067 ret
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@ -315,195 +313,319 @@ void redirectTrap(){
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csr_write(scause, csr_read(mcause));
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8000021c: 342027f3 csrr a5,mcause
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80000220: 14279073 csrw scause,a5
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csr_write(mepc, csr_read(stvec));
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80000224: 105027f3 csrr a5,stvec
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80000228: 34179073 csrw mepc,a5
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}
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80000224: 00c12083 lw ra,12(sp)
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80000228: 01010113 addi sp,sp,16
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8000022c: 00008067 ret
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8000022c: 00c12083 lw ra,12(sp)
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80000230: 01010113 addi sp,sp,16
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80000234: 00008067 ret
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80000238 <emulationTrapToSupervisorTrap>:
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void emulationTrapToSupervisorTrap(uint32_t sepc, uint32_t mstatus){
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csr_write(sbadaddr, csr_read(mbadaddr));
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80000238: 343027f3 csrr a5,mbadaddr
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8000023c: 14379073 csrw sbadaddr,a5
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csr_write(scause, csr_read(mcause));
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80000240: 342027f3 csrr a5,mcause
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80000244: 14279073 csrw scause,a5
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csr_write(sepc, sepc);
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80000248: 14151073 csrw sepc,a0
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csr_write(mepc, csr_read(stvec));
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8000024c: 105027f3 csrr a5,stvec
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80000250: 34179073 csrw mepc,a5
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csr_clear(sstatus, MSTATUS_SPP);
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80000254: 10000793 li a5,256
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80000258: 1007b073 csrc sstatus,a5
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csr_set(sstatus, (mstatus >> 3) & MSTATUS_SPP);
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8000025c: 0035d593 srli a1,a1,0x3
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80000260: 1005f593 andi a1,a1,256
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80000264: 1005a073 csrs sstatus,a1
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csr_clear(mstatus, MSTATUS_MPP);
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80000268: 000027b7 lui a5,0x2
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8000026c: 80078793 addi a5,a5,-2048 # 1800 <__stack_size+0x1000>
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80000270: 3007b073 csrc mstatus,a5
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csr_set(mstatus, 0x8000);
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80000274: 000087b7 lui a5,0x8
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80000278: 3007a073 csrs mstatus,a5
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}
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8000027c: 00008067 ret
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80000280 <readWord>:
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//Will modify MEPC
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int readWord(int address, int *data){
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int result, tmp;
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int failed;
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__asm__ __volatile__ (
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80000280: 00020737 lui a4,0x20
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80000284: 30072073 csrs mstatus,a4
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80000288: 00000717 auipc a4,0x0
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8000028c: 01870713 addi a4,a4,24 # 800002a0 <readWord+0x20>
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80000290: 34171073 csrw mepc,a4
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80000294: 00100693 li a3,1
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80000298: 00052783 lw a5,0(a0)
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8000029c: 00000693 li a3,0
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800002a0: 00020737 lui a4,0x20
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800002a4: 30073073 csrc mstatus,a4
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800002a8: 00068513 mv a0,a3
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: [result]"=&r" (result), [failed]"=&r" (failed), [tmp]"=&r" (tmp)
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: [address]"r" (address)
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: "memory"
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);
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*data = result;
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800002ac: 00f5a023 sw a5,0(a1)
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return failed;
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}
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800002b0: 00008067 ret
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800002b4 <writeWord>:
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//Will modify MEPC
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int writeWord(uint32_t address, uint32_t data){
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int result, tmp;
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int failed;
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__asm__ __volatile__ (
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800002b4: 00020737 lui a4,0x20
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800002b8: 30072073 csrs mstatus,a4
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800002bc: 00000717 auipc a4,0x0
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800002c0: 01870713 addi a4,a4,24 # 800002d4 <writeWord+0x20>
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800002c4: 34171073 csrw mepc,a4
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800002c8: 00100793 li a5,1
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800002cc: 00b52023 sw a1,0(a0)
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800002d0: 00000793 li a5,0
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800002d4: 00020737 lui a4,0x20
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800002d8: 30073073 csrc mstatus,a4
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800002dc: 00078513 mv a0,a5
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: [address]"r" (address), [data]"r" (data)
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: "memory"
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);
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return failed;
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}
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800002e0: 00008067 ret
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800002e4 <trap>:
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80000230 <trap>:
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#define min(a,b) \
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({ __typeof__ (a) _a = (a); \
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__typeof__ (b) _b = (b); \
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_a < _b ? _a : _b; })
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void trap(){
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80000230: fe010113 addi sp,sp,-32
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80000234: 00112e23 sw ra,28(sp)
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80000238: 00812c23 sw s0,24(sp)
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8000023c: 00912a23 sw s1,20(sp)
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80000240: 01212823 sw s2,16(sp)
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80000244: 01312623 sw s3,12(sp)
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800002e4: fd010113 addi sp,sp,-48
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800002e8: 02112623 sw ra,44(sp)
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800002ec: 02812423 sw s0,40(sp)
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800002f0: 02912223 sw s1,36(sp)
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800002f4: 03212023 sw s2,32(sp)
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800002f8: 01312e23 sw s3,28(sp)
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800002fc: 01412c23 sw s4,24(sp)
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80000300: 01512a23 sw s5,20(sp)
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int cause = csr_read(mcause);
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80000248: 342027f3 csrr a5,mcause
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80000304: 342027f3 csrr a5,mcause
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if(cause < 0){
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8000024c: 0207ca63 bltz a5,80000280 <trap+0x50>
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80000308: 0207ce63 bltz a5,80000344 <trap+0x60>
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redirectTrap();
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} else {
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switch(cause){
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80000250: 00200713 li a4,2
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80000254: 02e78a63 beq a5,a4,80000288 <trap+0x58>
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80000258: 00900713 li a4,9
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8000025c: 10e78863 beq a5,a4,8000036c <trap+0x13c>
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8000030c: 00200713 li a4,2
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80000310: 02e78e63 beq a5,a4,8000034c <trap+0x68>
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80000314: 00900713 li a4,9
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80000318: 16e78e63 beq a5,a4,80000494 <trap+0x1b0>
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csr_write(mepc, csr_read(mepc) + 4);
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}break;
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default: stopSim(); break;
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}
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}break;
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default: redirectTrap(); break;
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80000260: fa1ff0ef jal ra,80000200 <redirectTrap>
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8000031c: ee5ff0ef jal ra,80000200 <redirectTrap>
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}
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}
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}
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80000264: 01c12083 lw ra,28(sp)
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80000268: 01812403 lw s0,24(sp)
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8000026c: 01412483 lw s1,20(sp)
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80000270: 01012903 lw s2,16(sp)
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80000274: 00c12983 lw s3,12(sp)
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80000278: 02010113 addi sp,sp,32
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8000027c: 00008067 ret
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80000320: 02c12083 lw ra,44(sp)
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80000324: 02812403 lw s0,40(sp)
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80000328: 02412483 lw s1,36(sp)
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8000032c: 02012903 lw s2,32(sp)
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80000330: 01c12983 lw s3,28(sp)
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80000334: 01812a03 lw s4,24(sp)
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80000338: 01412a83 lw s5,20(sp)
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8000033c: 03010113 addi sp,sp,48
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80000340: 00008067 ret
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redirectTrap();
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80000280: f81ff0ef jal ra,80000200 <redirectTrap>
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80000284: fe1ff06f j 80000264 <trap+0x34>
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80000344: ebdff0ef jal ra,80000200 <redirectTrap>
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80000348: fd9ff06f j 80000320 <trap+0x3c>
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int mepc = csr_read(mepc);
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8000034c: 341024f3 csrr s1,mepc
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int mstatus = csr_read(mstatus);
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80000350: 300029f3 csrr s3,mstatus
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int instruction = csr_read(mbadaddr);
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80000288: 34302473 csrr s0,mbadaddr
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80000354: 34302473 csrr s0,mbadaddr
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int opcode = instruction & 0x7F;
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8000028c: 07f47693 andi a3,s0,127
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80000358: 07f47693 andi a3,s0,127
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int funct3 = (instruction >> 12) & 0x7;
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80000290: 40c45793 srai a5,s0,0xc
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80000294: 0077f793 andi a5,a5,7
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8000035c: 40c45793 srai a5,s0,0xc
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80000360: 0077f793 andi a5,a5,7
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switch(opcode){
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80000298: 02f00713 li a4,47
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8000029c: fce694e3 bne a3,a4,80000264 <trap+0x34>
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80000364: 02f00713 li a4,47
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80000368: fae69ce3 bne a3,a4,80000320 <trap+0x3c>
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switch(funct3){
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800002a0: 00200713 li a4,2
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800002a4: 0ce79063 bne a5,a4,80000364 <trap+0x134>
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8000036c: 00200713 li a4,2
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80000370: 10e79e63 bne a5,a4,8000048c <trap+0x1a8>
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int sel = instruction >> 27;
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800002a8: 41b45493 srai s1,s0,0x1b
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int*addr = (int*)readRegister((instruction >> 15) & 0x1F);
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800002ac: 40f45513 srai a0,s0,0xf
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800002b0: 01f57513 andi a0,a0,31
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800002b4: f0dff0ef jal ra,800001c0 <readRegister>
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800002b8: 00050993 mv s3,a0
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int src = readRegister((instruction >> 20) & 0x1F);
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800002bc: 41445513 srai a0,s0,0x14
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800002c0: 01f57513 andi a0,a0,31
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800002c4: efdff0ef jal ra,800001c0 <readRegister>
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800002c8: 00050913 mv s2,a0
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int rd = (instruction >> 7) & 0x1F;
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800002cc: 40745413 srai s0,s0,0x7
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800002d0: 01f47513 andi a0,s0,31
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int readValue = *addr;
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800002d4: 0009a583 lw a1,0(s3)
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switch(sel){
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800002d8: 01c00793 li a5,28
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800002dc: 0897e063 bltu a5,s1,8000035c <trap+0x12c>
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800002e0: 00249493 slli s1,s1,0x2
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800002e4: 800007b7 lui a5,0x80000
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800002e8: 43c78793 addi a5,a5,1084 # 8000043c <_sp+0xfffff78c>
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800002ec: 00f484b3 add s1,s1,a5
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800002f0: 0004a783 lw a5,0(s1)
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800002f4: 00078067 jr a5
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case 0x0: writeValue = src + readValue; break;
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800002f8: 00b90933 add s2,s2,a1
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||||
writeRegister(rd, readValue);
|
||||
800002fc: eddff0ef jal ra,800001d8 <writeRegister>
|
||||
*addr = writeValue;
|
||||
80000300: 0129a023 sw s2,0(s3)
|
||||
csr_write(mepc, csr_read(mepc) + 4);
|
||||
80000304: 341027f3 csrr a5,mepc
|
||||
80000308: 00478793 addi a5,a5,4
|
||||
8000030c: 34179073 csrw mepc,a5
|
||||
}break;
|
||||
80000310: f55ff06f j 80000264 <trap+0x34>
|
||||
case 0x4: writeValue = src ^ readValue; break;
|
||||
80000314: 00b94933 xor s2,s2,a1
|
||||
80000318: fe5ff06f j 800002fc <trap+0xcc>
|
||||
case 0xC: writeValue = src & readValue; break;
|
||||
8000031c: 00b97933 and s2,s2,a1
|
||||
80000320: fddff06f j 800002fc <trap+0xcc>
|
||||
case 0x8: writeValue = src | readValue; break;
|
||||
80000324: 00b96933 or s2,s2,a1
|
||||
80000328: fd5ff06f j 800002fc <trap+0xcc>
|
||||
case 0x10: writeValue = min(src, readValue); break;
|
||||
8000032c: fd25d8e3 ble s2,a1,800002fc <trap+0xcc>
|
||||
80000330: 00058913 mv s2,a1
|
||||
80000334: fc9ff06f j 800002fc <trap+0xcc>
|
||||
case 0x14: writeValue = max(src, readValue); break;
|
||||
80000338: fcb952e3 ble a1,s2,800002fc <trap+0xcc>
|
||||
8000033c: 00058913 mv s2,a1
|
||||
80000340: fbdff06f j 800002fc <trap+0xcc>
|
||||
case 0x18: writeValue = min((unsigned int)src, (unsigned int)readValue); break;
|
||||
80000344: fb25fce3 bleu s2,a1,800002fc <trap+0xcc>
|
||||
80000348: 00058913 mv s2,a1
|
||||
8000034c: fb1ff06f j 800002fc <trap+0xcc>
|
||||
case 0x1C: writeValue = max((unsigned int)src, (unsigned int)readValue); break;
|
||||
80000350: fab976e3 bleu a1,s2,800002fc <trap+0xcc>
|
||||
80000354: 00058913 mv s2,a1
|
||||
80000358: fa5ff06f j 800002fc <trap+0xcc>
|
||||
default: redirectTrap(); return; break;
|
||||
8000035c: ea5ff0ef jal ra,80000200 <redirectTrap>
|
||||
80000360: f05ff06f j 80000264 <trap+0x34>
|
||||
default: redirectTrap(); break;
|
||||
80000364: e9dff0ef jal ra,80000200 <redirectTrap>
|
||||
80000368: efdff06f j 80000264 <trap+0x34>
|
||||
int which = readRegister(17);
|
||||
8000036c: 01100513 li a0,17
|
||||
80000370: e51ff0ef jal ra,800001c0 <readRegister>
|
||||
switch(which){
|
||||
80000374: 00100793 li a5,1
|
||||
80000378: 02f51263 bne a0,a5,8000039c <trap+0x16c>
|
||||
putC(readRegister(10));
|
||||
8000037c: 00a00513 li a0,10
|
||||
80000374: 41b45913 srai s2,s0,0x1b
|
||||
int addr = readRegister((instruction >> 15) & 0x1F);
|
||||
80000378: 40f45513 srai a0,s0,0xf
|
||||
8000037c: 01f57513 andi a0,a0,31
|
||||
80000380: e41ff0ef jal ra,800001c0 <readRegister>
|
||||
80000384: 0ff57513 andi a0,a0,255
|
||||
80000388: e71ff0ef jal ra,800001f8 <putC>
|
||||
80000384: 00050a93 mv s5,a0
|
||||
int src = readRegister((instruction >> 20) & 0x1F);
|
||||
80000388: 41445513 srai a0,s0,0x14
|
||||
8000038c: 01f57513 andi a0,a0,31
|
||||
80000390: e31ff0ef jal ra,800001c0 <readRegister>
|
||||
80000394: 00050a13 mv s4,a0
|
||||
int rd = (instruction >> 7) & 0x1F;
|
||||
80000398: 40745413 srai s0,s0,0x7
|
||||
8000039c: 01f47413 andi s0,s0,31
|
||||
if(readWord(addr, &readValue)){
|
||||
800003a0: 00c10593 addi a1,sp,12
|
||||
800003a4: 000a8513 mv a0,s5
|
||||
800003a8: ed9ff0ef jal ra,80000280 <readWord>
|
||||
800003ac: 02051263 bnez a0,800003d0 <trap+0xec>
|
||||
switch(sel){
|
||||
800003b0: 01c00793 li a5,28
|
||||
800003b4: 0d27e063 bltu a5,s2,80000474 <trap+0x190>
|
||||
800003b8: 00291913 slli s2,s2,0x2
|
||||
800003bc: 800007b7 lui a5,0x80000
|
||||
800003c0: 56478793 addi a5,a5,1380 # 80000564 <_sp+0xfffff78c>
|
||||
800003c4: 00f90933 add s2,s2,a5
|
||||
800003c8: 00092783 lw a5,0(s2)
|
||||
800003cc: 00078067 jr a5
|
||||
emulationTrapToSupervisorTrap(mepc, mstatus);
|
||||
800003d0: 00098593 mv a1,s3
|
||||
800003d4: 00048513 mv a0,s1
|
||||
800003d8: e61ff0ef jal ra,80000238 <emulationTrapToSupervisorTrap>
|
||||
return;
|
||||
800003dc: f45ff06f j 80000320 <trap+0x3c>
|
||||
case 0x0: writeValue = src + readValue; break;
|
||||
800003e0: 00c12783 lw a5,12(sp)
|
||||
800003e4: 00fa0a33 add s4,s4,a5
|
||||
writeRegister(rd, readValue);
|
||||
800003e8: 00c12583 lw a1,12(sp)
|
||||
800003ec: 00040513 mv a0,s0
|
||||
800003f0: de9ff0ef jal ra,800001d8 <writeRegister>
|
||||
if(writeWord(addr, writeValue)){
|
||||
800003f4: 000a0593 mv a1,s4
|
||||
800003f8: 000a8513 mv a0,s5
|
||||
800003fc: eb9ff0ef jal ra,800002b4 <writeWord>
|
||||
80000400: 06051e63 bnez a0,8000047c <trap+0x198>
|
||||
csr_write(mepc, mepc + 4);
|
||||
80000404: 00448493 addi s1,s1,4
|
||||
80000408: 34149073 csrw mepc,s1
|
||||
}break;
|
||||
8000040c: f15ff06f j 80000320 <trap+0x3c>
|
||||
case 0x4: writeValue = src ^ readValue; break;
|
||||
80000410: 00c12783 lw a5,12(sp)
|
||||
80000414: 00fa4a33 xor s4,s4,a5
|
||||
80000418: fd1ff06f j 800003e8 <trap+0x104>
|
||||
case 0xC: writeValue = src & readValue; break;
|
||||
8000041c: 00c12783 lw a5,12(sp)
|
||||
80000420: 00fa7a33 and s4,s4,a5
|
||||
80000424: fc5ff06f j 800003e8 <trap+0x104>
|
||||
case 0x8: writeValue = src | readValue; break;
|
||||
80000428: 00c12783 lw a5,12(sp)
|
||||
8000042c: 00fa6a33 or s4,s4,a5
|
||||
80000430: fb9ff06f j 800003e8 <trap+0x104>
|
||||
case 0x10: writeValue = min(src, readValue); break;
|
||||
80000434: 00c12783 lw a5,12(sp)
|
||||
80000438: fb47d8e3 ble s4,a5,800003e8 <trap+0x104>
|
||||
8000043c: 00078a13 mv s4,a5
|
||||
80000440: fa9ff06f j 800003e8 <trap+0x104>
|
||||
case 0x14: writeValue = max(src, readValue); break;
|
||||
80000444: 00c12783 lw a5,12(sp)
|
||||
80000448: fafa50e3 ble a5,s4,800003e8 <trap+0x104>
|
||||
8000044c: 00078a13 mv s4,a5
|
||||
80000450: f99ff06f j 800003e8 <trap+0x104>
|
||||
case 0x18: writeValue = min((unsigned int)src, (unsigned int)readValue); break;
|
||||
80000454: 00c12783 lw a5,12(sp)
|
||||
80000458: f947f8e3 bleu s4,a5,800003e8 <trap+0x104>
|
||||
8000045c: 00078a13 mv s4,a5
|
||||
80000460: f89ff06f j 800003e8 <trap+0x104>
|
||||
case 0x1C: writeValue = max((unsigned int)src, (unsigned int)readValue); break;
|
||||
80000464: 00c12783 lw a5,12(sp)
|
||||
80000468: f8fa70e3 bleu a5,s4,800003e8 <trap+0x104>
|
||||
8000046c: 00078a13 mv s4,a5
|
||||
80000470: f79ff06f j 800003e8 <trap+0x104>
|
||||
default: redirectTrap(); return; break;
|
||||
80000474: d8dff0ef jal ra,80000200 <redirectTrap>
|
||||
80000478: ea9ff06f j 80000320 <trap+0x3c>
|
||||
emulationTrapToSupervisorTrap(mepc, mstatus);
|
||||
8000047c: 00098593 mv a1,s3
|
||||
80000480: 00048513 mv a0,s1
|
||||
80000484: db5ff0ef jal ra,80000238 <emulationTrapToSupervisorTrap>
|
||||
return;
|
||||
80000488: e99ff06f j 80000320 <trap+0x3c>
|
||||
default: redirectTrap(); break;
|
||||
8000048c: d75ff0ef jal ra,80000200 <redirectTrap>
|
||||
80000490: e91ff06f j 80000320 <trap+0x3c>
|
||||
int which = readRegister(17);
|
||||
80000494: 01100513 li a0,17
|
||||
80000498: d29ff0ef jal ra,800001c0 <readRegister>
|
||||
switch(which){
|
||||
8000049c: 00100793 li a5,1
|
||||
800004a0: 02f51263 bne a0,a5,800004c4 <trap+0x1e0>
|
||||
putC(readRegister(10));
|
||||
800004a4: 00a00513 li a0,10
|
||||
800004a8: d19ff0ef jal ra,800001c0 <readRegister>
|
||||
800004ac: 0ff57513 andi a0,a0,255
|
||||
800004b0: d49ff0ef jal ra,800001f8 <putC>
|
||||
csr_write(mepc, csr_read(mepc) + 4);
|
||||
8000038c: 341027f3 csrr a5,mepc
|
||||
80000390: 00478793 addi a5,a5,4
|
||||
80000394: 34179073 csrw mepc,a5
|
||||
800004b4: 341027f3 csrr a5,mepc
|
||||
800004b8: 00478793 addi a5,a5,4
|
||||
800004bc: 34179073 csrw mepc,a5
|
||||
}break;
|
||||
80000398: ecdff06f j 80000264 <trap+0x34>
|
||||
800004c0: e61ff06f j 80000320 <trap+0x3c>
|
||||
default: stopSim(); break;
|
||||
8000039c: e55ff0ef jal ra,800001f0 <stopSim>
|
||||
800003a0: ec5ff06f j 80000264 <trap+0x34>
|
||||
800004c4: d2dff0ef jal ra,800001f0 <stopSim>
|
||||
800004c8: e59ff06f j 80000320 <trap+0x3c>
|
||||
|
||||
800003a4 <__libc_init_array>:
|
||||
800003a4: ff010113 addi sp,sp,-16
|
||||
800003a8: 00812423 sw s0,8(sp)
|
||||
800003ac: 00912223 sw s1,4(sp)
|
||||
800003b0: 00000417 auipc s0,0x0
|
||||
800003b4: 08c40413 addi s0,s0,140 # 8000043c <__init_array_end>
|
||||
800003b8: 00000497 auipc s1,0x0
|
||||
800003bc: 08448493 addi s1,s1,132 # 8000043c <__init_array_end>
|
||||
800003c0: 408484b3 sub s1,s1,s0
|
||||
800003c4: 01212023 sw s2,0(sp)
|
||||
800003c8: 00112623 sw ra,12(sp)
|
||||
800003cc: 4024d493 srai s1,s1,0x2
|
||||
800003d0: 00000913 li s2,0
|
||||
800003d4: 04991063 bne s2,s1,80000414 <__libc_init_array+0x70>
|
||||
800003d8: 00000417 auipc s0,0x0
|
||||
800003dc: 06440413 addi s0,s0,100 # 8000043c <__init_array_end>
|
||||
800003e0: 00000497 auipc s1,0x0
|
||||
800003e4: 05c48493 addi s1,s1,92 # 8000043c <__init_array_end>
|
||||
800003e8: 408484b3 sub s1,s1,s0
|
||||
800003ec: c8dff0ef jal ra,80000078 <_init>
|
||||
800003f0: 4024d493 srai s1,s1,0x2
|
||||
800003f4: 00000913 li s2,0
|
||||
800003f8: 02991863 bne s2,s1,80000428 <__libc_init_array+0x84>
|
||||
800003fc: 00c12083 lw ra,12(sp)
|
||||
80000400: 00812403 lw s0,8(sp)
|
||||
80000404: 00412483 lw s1,4(sp)
|
||||
80000408: 00012903 lw s2,0(sp)
|
||||
8000040c: 01010113 addi sp,sp,16
|
||||
80000410: 00008067 ret
|
||||
80000414: 00042783 lw a5,0(s0)
|
||||
80000418: 00190913 addi s2,s2,1
|
||||
8000041c: 00440413 addi s0,s0,4
|
||||
80000420: 000780e7 jalr a5
|
||||
80000424: fb1ff06f j 800003d4 <__libc_init_array+0x30>
|
||||
80000428: 00042783 lw a5,0(s0)
|
||||
8000042c: 00190913 addi s2,s2,1
|
||||
80000430: 00440413 addi s0,s0,4
|
||||
80000434: 000780e7 jalr a5
|
||||
80000438: fc1ff06f j 800003f8 <__libc_init_array+0x54>
|
||||
800004cc <__libc_init_array>:
|
||||
800004cc: ff010113 addi sp,sp,-16
|
||||
800004d0: 00812423 sw s0,8(sp)
|
||||
800004d4: 00912223 sw s1,4(sp)
|
||||
800004d8: 00000417 auipc s0,0x0
|
||||
800004dc: 08c40413 addi s0,s0,140 # 80000564 <__init_array_end>
|
||||
800004e0: 00000497 auipc s1,0x0
|
||||
800004e4: 08448493 addi s1,s1,132 # 80000564 <__init_array_end>
|
||||
800004e8: 408484b3 sub s1,s1,s0
|
||||
800004ec: 01212023 sw s2,0(sp)
|
||||
800004f0: 00112623 sw ra,12(sp)
|
||||
800004f4: 4024d493 srai s1,s1,0x2
|
||||
800004f8: 00000913 li s2,0
|
||||
800004fc: 04991063 bne s2,s1,8000053c <__libc_init_array+0x70>
|
||||
80000500: 00000417 auipc s0,0x0
|
||||
80000504: 06440413 addi s0,s0,100 # 80000564 <__init_array_end>
|
||||
80000508: 00000497 auipc s1,0x0
|
||||
8000050c: 05c48493 addi s1,s1,92 # 80000564 <__init_array_end>
|
||||
80000510: 408484b3 sub s1,s1,s0
|
||||
80000514: b65ff0ef jal ra,80000078 <_init>
|
||||
80000518: 4024d493 srai s1,s1,0x2
|
||||
8000051c: 00000913 li s2,0
|
||||
80000520: 02991863 bne s2,s1,80000550 <__libc_init_array+0x84>
|
||||
80000524: 00c12083 lw ra,12(sp)
|
||||
80000528: 00812403 lw s0,8(sp)
|
||||
8000052c: 00412483 lw s1,4(sp)
|
||||
80000530: 00012903 lw s2,0(sp)
|
||||
80000534: 01010113 addi sp,sp,16
|
||||
80000538: 00008067 ret
|
||||
8000053c: 00042783 lw a5,0(s0)
|
||||
80000540: 00190913 addi s2,s2,1
|
||||
80000544: 00440413 addi s0,s0,4
|
||||
80000548: 000780e7 jalr a5
|
||||
8000054c: fb1ff06f j 800004fc <__libc_init_array+0x30>
|
||||
80000550: 00042783 lw a5,0(s0)
|
||||
80000554: 00190913 addi s2,s2,1
|
||||
80000558: 00440413 addi s0,s0,4
|
||||
8000055c: 000780e7 jalr a5
|
||||
80000560: fc1ff06f j 80000520 <__libc_init_array+0x54>
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
:0200000480007A
|
||||
:1000000017110000130101CB17050000130545432C
|
||||
:10001000970500009385C542170600001306864920
|
||||
:1000000017110000130181DD170500001305C55508
|
||||
:100010009705000093854555170600001306065CFA
|
||||
:1000200063FCC5008322050023A05500130545008D
|
||||
:1000300093854500E3E8C5FE1705000013058547D5
|
||||
:1000400097050000938505476378B50023200500D8
|
||||
:1000500013054500E36CB5FEEF00C034EF008012DD
|
||||
:1000300093854500E3E8C5FE170500001305055A42
|
||||
:1000400097050000938585596378B5002320050046
|
||||
:1000500013054500E36CB5FEEF004047EF0080124A
|
||||
:100060009700000093804001370500819305000050
|
||||
:10007000730020306F0000006780000073110134AE
|
||||
:1000800023200100232211002326310023284100D0
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
:1000C0002322110523242105232631052328410558
|
||||
:1000D000232A5105232C6105232E71052320810736
|
||||
:1000E000232291072324A1072326B1072328C10730
|
||||
:1000F000232AD107232CE107232EF107EF00401319
|
||||
:1000F000232AD107232CE107232EF107EF00801ECE
|
||||
:1001000003200100832041008321C100032201015B
|
||||
:1001100083224101032381018323C10103240102BE
|
||||
:1001200083244102032581028325C10203260103A2
|
||||
|
|
@ -25,56 +25,74 @@
|
|||
:10017000832E4107032F8107832FC1077311013499
|
||||
:0401800073002030B8
|
||||
:10018400B70700809387C70773905730B71700806D
|
||||
:10019400938707CB938707F873900734B71700004A
|
||||
:10019400938787DD938707F873900734B7170000B8
|
||||
:1001A4009387078073900730B70700C073901734A4
|
||||
:1001B400B7B700007390273067800000131525003F
|
||||
:1001C400B7170080938707CB3305F500032505F89F
|
||||
:1001D4006780000013152500B7170080938707CBAD
|
||||
:1001C400B7170080938787DD3305F500032505F80D
|
||||
:1001D4006780000013152500B7170080938787DD1B
|
||||
:1001E4003305F5002320B5F867800000232E00FEB8
|
||||
:1001F40067800000232CA0FE67800000130101FF2C
|
||||
:1002040023261100EFF09FFEF32730347390371448
|
||||
:10021400F327103473901714F327203473902714A2
|
||||
:100224008320C1001301010167800000130101FE56
|
||||
:10023400232E1100232C8100232A9100232821013D
|
||||
:1002440023263101F327203463CA07021307200051
|
||||
:10025400638AE702130790006388E710EFF01FFA40
|
||||
:100264008320C10103248101832441010329010165
|
||||
:100274008329C1001301010267800000EFF01FF819
|
||||
:100284006FF01FFE732430349376F4079357C44001
|
||||
:1002940093F777001307F002E394E6FC13072000BA
|
||||
:1002A4006390E70C9354B4411355F4401375F5016E
|
||||
:1002B400EFF0DFF093090500135544411375F50180
|
||||
:1002C400EFF0DFEF13090500135474401375F401C4
|
||||
:1002D40083A509009307C00163E097089394240061
|
||||
:1002E400B70700809387C743B384F40083A704004F
|
||||
:1002F400678007003309B900EFF0DFED23A029017F
|
||||
:10030400F327103493874700739017346FF05FF529
|
||||
:100314003349B9006FF05FFE3379B9006FF0DFFD48
|
||||
:100324003369B9006FF05FFDE3D825FD138905003B
|
||||
:100334006FF09FFCE352B9FC138905006FF0DFFBFB
|
||||
:10034400E3FC25FB138905006FF01FFBE376B9FA84
|
||||
:10035400138905006FF05FFAEFF05FEA6FF05FF06A
|
||||
:10036400EFF0DFE96FF0DFEF13051001EFF01FE5A9
|
||||
:10037400930710006312F5021305A000EFF01FE4C9
|
||||
:100384001375F50FEFF01FE7F32710349387470039
|
||||
:10039400739017346FF0DFECEFF05FE56FF05FEC14
|
||||
:1003A400130101FF2324810023229100170400007C
|
||||
:1003B4001304C4089704000093844408B38484405D
|
||||
:1003C400232021012326110093D424401309000083
|
||||
:1003D40063109904170400001304440697040000F2
|
||||
:1003E4009384C405B3848440EFF0DFC893D42440DD
|
||||
:1003F40013090000631899028320C10003248100BB
|
||||
:1004040083244100032901001301010167800000D6
|
||||
:10041400832704001309190013044400E78007002C
|
||||
:100424006FF01FFB83270400130919001304440011
|
||||
:08043400E78007006FF01FFCD8
|
||||
:10043C00F8020080FC0200805C0300805C030080FA
|
||||
:10044C00140300805C0300805C0300805C0300806C
|
||||
:10045C00240300805C0300805C0300805C0300804C
|
||||
:10046C001C0300805C0300805C0300805C03008044
|
||||
:10047C002C0300805C0300805C0300805C03008024
|
||||
:10048C00380300805C0300805C0300805C03008008
|
||||
:10049C00440300805C0300805C0300805C030080EC
|
||||
:0404AC005003008079
|
||||
:10022400F3275010739017348320C1001301010188
|
||||
:1002340067800000F327303473903714F327203499
|
||||
:100244007390271473101514F327501073901734F8
|
||||
:100254009307001073B0071093D5350093F505107C
|
||||
:1002640073A00510B72700009387078073B0073089
|
||||
:10027400B787000073A007306780000037070200CB
|
||||
:100284007320073017070000130787017310173412
|
||||
:100294009306100083270500930600003707020029
|
||||
:1002A400733007301385060023A0F5006780000033
|
||||
:1002B4003707020073200730170700001307870170
|
||||
:1002C40073101734930710002320B5009307000020
|
||||
:1002D400370702007330073013850700678000007A
|
||||
:1002E400130101FD232611022324810223229102FA
|
||||
:1002F40023202103232E3101232C4101232A5101E0
|
||||
:10030400F327203463CE070213072000638EE7022D
|
||||
:1003140013079000638EE716EFF05FEE8320C102AF
|
||||
:100324000324810283244102032901028329C10198
|
||||
:10033400032A8101832A410113010103678000001C
|
||||
:10034400EFF0DFEB6FF09FFDF3241034F32900305E
|
||||
:10035400732430349376F4079357C44093F77700AB
|
||||
:100364001307F002E39CE6FA13072000639EE710EC
|
||||
:100374001359B4411355F4401375F501EFF01FE41C
|
||||
:10038400930A0500135544411375F501EFF01FE37B
|
||||
:10039400130A0500135474401374F4019305C10047
|
||||
:1003A40013850A00EFF09FED631205029307C00165
|
||||
:1003B40063E0270D13192900B70700809387475678
|
||||
:1003C4003309F90083270900678007009385090032
|
||||
:1003D40013850400EFF01FE66FF05FF48327C1007C
|
||||
:1003E400330AFA008325C10013050400EFF09FDEF1
|
||||
:1003F40093050A0013850A00EFF09FEB631E0506C0
|
||||
:1004040093844400739014346FF05FF18327C10028
|
||||
:10041400334AFA006FF01FFD8327C100337AFA00D4
|
||||
:100424006FF05FFC8327C100336AFA006FF09FFB13
|
||||
:100434008327C100E3D847FB138A07006FF09FFAB4
|
||||
:100444008327C100E350FAFA138A07006FF09FF97B
|
||||
:100454008327C100E3F847F9138A07006FF09FF878
|
||||
:100464008327C100E370FAF8138A07006FF09FF73F
|
||||
:10047400EFF0DFD86FF09FEA93850900138504003D
|
||||
:10048400EFF05FDB6FF09FE9EFF05FD76FF01FE9EC
|
||||
:1004940013051001EFF09FD2930710006312F502C9
|
||||
:1004A4001305A000EFF09FD11375F50FEFF09FD463
|
||||
:1004B400F327103493874700739017346FF01FE6C7
|
||||
:1004C400EFF0DFD26FF09FE5130101FF23248100D9
|
||||
:1004D40023229100170400001304C40897040000A9
|
||||
:1004E40093844408B38484402320210123261100EB
|
||||
:1004F40093D42440130900006310990417040000E6
|
||||
:1005040013044406970400009384C405B384844010
|
||||
:10051400EFF05FB693D424401309000063189902E6
|
||||
:100524008320C100032481008324410003290100A6
|
||||
:1005340013010101678000008327040013091900D7
|
||||
:1005440013044400E78007006FF01FFB83270400B7
|
||||
:100554001309190013044400E78007006FF01FFC1F
|
||||
:10056400E0030080E80300807404008074040080C9
|
||||
:1005740010040080740400807404008074040080FB
|
||||
:1005840028040080740400807404008074040080D3
|
||||
:100594001C040080740400807404008074040080CF
|
||||
:1005A40034040080740400807404008074040080A7
|
||||
:1005B4004404008074040080740400807404008087
|
||||
:1005C4005404008074040080740400807404008067
|
||||
:0405D400640400803B
|
||||
:040000058000000077
|
||||
:00000001FF
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@
|
|||
|
||||
extern const unsigned int _sp;
|
||||
extern void trapEntry();
|
||||
extern void emulationTrap();
|
||||
|
||||
void init() {
|
||||
csr_write(mtvec, trapEntry);
|
||||
|
||||
unsigned int sp = (unsigned int) (&_sp);
|
||||
csr_write(mtvec, trapEntry);
|
||||
csr_write(mscratch, sp -32*4);
|
||||
csr_write(mstatus, 0x0800);
|
||||
csr_write(mepc, OS_CALL);
|
||||
|
|
@ -39,6 +39,18 @@ void redirectTrap(){
|
|||
csr_write(sbadaddr, csr_read(mbadaddr));
|
||||
csr_write(sepc, csr_read(mepc));
|
||||
csr_write(scause, csr_read(mcause));
|
||||
csr_write(mepc, csr_read(stvec));
|
||||
}
|
||||
|
||||
void emulationTrapToSupervisorTrap(uint32_t sepc, uint32_t mstatus){
|
||||
csr_write(sbadaddr, csr_read(mbadaddr));
|
||||
csr_write(scause, csr_read(mcause));
|
||||
csr_write(sepc, sepc);
|
||||
csr_write(mepc, csr_read(stvec));
|
||||
csr_clear(sstatus, MSTATUS_SPP);
|
||||
csr_set(sstatus, (mstatus >> 3) & MSTATUS_SPP);
|
||||
csr_clear(mstatus, MSTATUS_MPP);
|
||||
csr_set(mstatus, 0x8000);
|
||||
}
|
||||
|
||||
#define max(a,b) \
|
||||
|
|
@ -52,6 +64,61 @@ void redirectTrap(){
|
|||
__typeof__ (b) _b = (b); \
|
||||
_a < _b ? _a : _b; })
|
||||
|
||||
|
||||
|
||||
//Will modify MEPC
|
||||
int readWord(int address, int *data){
|
||||
int result, tmp;
|
||||
int failed;
|
||||
__asm__ __volatile__ (
|
||||
" li %[tmp], 0x00020000\n"
|
||||
" csrs mstatus, %[tmp]\n"
|
||||
" la %[tmp], 1f\n"
|
||||
" csrw mepc, %[tmp]\n"
|
||||
" li %[failed], 1\n"
|
||||
" lw %[result], 0(%[address])\n"
|
||||
" li %[failed], 0\n"
|
||||
"1:\n"
|
||||
" li %[tmp], 0x00020000\n"
|
||||
" csrc mstatus, %[tmp]\n"
|
||||
: [result]"=&r" (result), [failed]"=&r" (failed), [tmp]"=&r" (tmp)
|
||||
: [address]"r" (address)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
*data = result;
|
||||
return failed;
|
||||
}
|
||||
|
||||
//Will modify MEPC
|
||||
int writeWord(uint32_t address, uint32_t data){
|
||||
int result, tmp;
|
||||
int failed;
|
||||
__asm__ __volatile__ (
|
||||
" li %[tmp], 0x00020000\n"
|
||||
" csrs mstatus, %[tmp]\n"
|
||||
" la %[tmp], 1f\n"
|
||||
" csrw mepc, %[tmp]\n"
|
||||
" li %[failed], 1\n"
|
||||
" sw %[data], 0(%[address])\n"
|
||||
" li %[failed], 0\n"
|
||||
"1:\n"
|
||||
" li %[tmp], 0x00020000\n"
|
||||
" csrc mstatus, %[tmp]\n"
|
||||
: [failed]"=&r" (failed), [tmp]"=&r" (tmp)
|
||||
: [address]"r" (address), [data]"r" (data)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return failed;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void trap(){
|
||||
int cause = csr_read(mcause);
|
||||
if(cause < 0){
|
||||
|
|
@ -59,6 +126,8 @@ void trap(){
|
|||
} else {
|
||||
switch(cause){
|
||||
case CAUSE_ILLEGAL_INSTRUCTION:{
|
||||
int mepc = csr_read(mepc);
|
||||
int mstatus = csr_read(mstatus);
|
||||
int instruction = csr_read(mbadaddr);
|
||||
int opcode = instruction & 0x7F;
|
||||
int funct3 = (instruction >> 12) & 0x7;
|
||||
|
|
@ -67,10 +136,14 @@ void trap(){
|
|||
switch(funct3){
|
||||
case 0x2:{
|
||||
int sel = instruction >> 27;
|
||||
int*addr = (int*)readRegister((instruction >> 15) & 0x1F);
|
||||
int addr = readRegister((instruction >> 15) & 0x1F);
|
||||
int src = readRegister((instruction >> 20) & 0x1F);
|
||||
int rd = (instruction >> 7) & 0x1F;
|
||||
int readValue = *addr;
|
||||
int readValue;
|
||||
if(readWord(addr, &readValue)){
|
||||
emulationTrapToSupervisorTrap(mepc, mstatus);
|
||||
return;
|
||||
}
|
||||
int writeValue;
|
||||
switch(sel){
|
||||
case 0x0: writeValue = src + readValue; break;
|
||||
|
|
@ -85,8 +158,11 @@ void trap(){
|
|||
default: redirectTrap(); return; break;
|
||||
}
|
||||
writeRegister(rd, readValue);
|
||||
*addr = writeValue;
|
||||
csr_write(mepc, csr_read(mepc) + 4);
|
||||
if(writeWord(addr, writeValue)){
|
||||
emulationTrapToSupervisorTrap(mepc, mstatus);
|
||||
return;
|
||||
}
|
||||
csr_write(mepc, mepc + 4);
|
||||
}break;
|
||||
default: redirectTrap(); break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -69,3 +69,5 @@ trapEntry:
|
|||
lw x31, 31*4(sp)
|
||||
csrrw sp, mscratch, sp
|
||||
mret
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -110,7 +110,13 @@ class MmuPlugin(virtualRange : UInt => Bool,
|
|||
val requireMmuLockup = virtualRange(port.bus.cmd.virtualAddress) && !port.bus.cmd.bypassTranslation && csr.satp.mode
|
||||
if(!allowMachineModeMmu) {
|
||||
requireMmuLockup clearWhen(!csr.status.mprv && privilegeService.isMachine())
|
||||
if(port.priority != MmuPort.PRIORITY_DATA) requireMmuLockup clearWhen(csr.status.mprv && pipeline(config.MPP) === 3)
|
||||
when(privilegeService.isMachine()) {
|
||||
if (port.priority == MmuPort.PRIORITY_DATA) {
|
||||
requireMmuLockup clearWhen (!csr.status.mprv)
|
||||
} else {
|
||||
requireMmuLockup := False
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
when(requireMmuLockup) {
|
||||
|
|
|
|||
|
|
@ -256,7 +256,8 @@ public:
|
|||
uint32_t spp : 1;
|
||||
uint32_t _3 : 2;
|
||||
uint32_t mpp : 2;
|
||||
uint32_t _4 : 5;
|
||||
uint32_t _4 : 4;
|
||||
uint32_t mprv : 1;
|
||||
uint32_t sum : 1;
|
||||
uint32_t mxr : 1;
|
||||
};
|
||||
|
|
@ -412,7 +413,8 @@ public:
|
|||
|
||||
enum AccessKind {READ,WRITE,EXECUTE};
|
||||
bool v2p(uint32_t v, uint32_t *p, AccessKind kind){
|
||||
if(privilege == 3 || satp.mode == 0){
|
||||
uint32_t effectivePrivilege = status.mprv && kind != EXECUTE ? status.mpp : privilege;
|
||||
if(effectivePrivilege == 3 || satp.mode == 0){
|
||||
*p = v;
|
||||
} else {
|
||||
Tlb tlb;
|
||||
|
|
@ -424,8 +426,8 @@ public:
|
|||
if(!tlb.v) return true;
|
||||
superPage = false;
|
||||
}
|
||||
if(!tlb.u && privilege == 0) return true;
|
||||
if( tlb.u && privilege == 1 && !status.sum) return true;
|
||||
if(!tlb.u && effectivePrivilege == 0) return true;
|
||||
if( tlb.u && effectivePrivilege == 1 && !status.sum) return true;
|
||||
if(superPage && tlb.ppn0 != 0) return true;
|
||||
switch(kind){
|
||||
case READ: if(!tlb.r && !(status.mxr && tlb.x)) return true; break;
|
||||
|
|
|
|||
|
|
@ -40,9 +40,9 @@ class PlicBench(inputCount : Int) extends Component{
|
|||
io.cpuInterrupt := targets(0).iep
|
||||
|
||||
val plicMapping = PlicMapping.light.copy(
|
||||
// gatewayPriorityReadGen = true,
|
||||
// gatewayPendingReadGen = true,
|
||||
// targetThresholdReadGen = true
|
||||
// gatewayPriorityReadGen = true,
|
||||
// gatewayPendingReadGen = true,
|
||||
// targetThresholdReadGen = true
|
||||
)
|
||||
|
||||
gateways.foreach(_.priority := 1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue