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Fix Bmb datacache bridge

This commit is contained in:
Charles Papon 2019-05-24 00:22:58 +02:00
parent f6f94ad7c1
commit 206c7ca638
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/ip/DataCache.scala
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@ -323,7 +323,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ)) bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
bus.cmd.address := cmd.address.resized bus.cmd.address := cmd.address.resized
bus.cmd.data := cmd.data bus.cmd.data := cmd.data
bus.cmd.length := cmd.length << 2 //TODO better sub word access bus.cmd.length := (cmd.length << 2) | 3 //TODO better sub word access
bus.cmd.mask := cmd.mask bus.cmd.mask := cmd.mask
cmd.ready := bus.cmd.ready cmd.ready := bus.cmd.ready