RISC-V debug havereset implemented

2022-11-10 15:49:03 +01:00 · 2022-11-10 15:49:03 +01:00 · 2504f9b9b9
parent 0bfaf06a4a
commit 2504f9b9b9
1 changed files with 4 additions and 0 deletions
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@ -696,6 +696,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
      bus.running :=  running
      bus.halted  := !running
      bus.unavailable := RegNext(ClockDomain.current.isResetActive)
+
+      val reseting   = RegNext(False) init(True)
+      bus.haveReset := RegInit(False) setWhen(reseting) clearWhen(bus.ackReset)
+
      val enterHalt = running.getAheadValue().fall(False)

      val doHalt = RegInit(False) setWhen(bus.haltReq && bus.running && !debugMode) clearWhen(enterHalt)