Add cache Bandwidth counter, previous commit was about random instruction cache way allocation

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -168,6 +168,14 @@ class DBusCachedPlugin(val config : DataCacheConfig,
     dBus.cmd << optionPipe(dBusCmdMasterPipe, cmdBuf)(_.m2sPipe())
     cache.io.mem.rsp << optionPipe(dBusRspSlavePipe,dBus.rsp)(_.m2sPipe())
 
+    pipeline plug new Area{
+      //Memory bandwidth counter
+      val rspCounter = RegInit(UInt(32 bits)) init(0)
+      when(dBus.rsp.valid){
+        rspCounter := rspCounter + 1
+      }
+    }
+
     decode plug new Area {
       import decode._
 

src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala

@@ -129,7 +129,13 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
       iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
       iBus <> cache.io.mem
       iBus.cmd.address.allowOverride := cache.io.mem.cmd.address
-      
+
+      //Memory bandwidth counter
+      val rspCounter = RegInit(UInt(32 bits)) init(0)
+      when(iBus.rsp.valid){
+        rspCounter := rspCounter + 1
+      }
+
       val stageOffset = if(relaxedPcCalculation) 1 else 0
       def stages = iBusRsp.stages.drop(stageOffset)