Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add cache Bandwidth counter, previous commit was about random instruction cache way allocation

This commit is contained in:
Charles Papon 2019-05-25 00:22:27 +02:00
parent 94606d38e2
commit 4a40184b35
2 changed files with 15 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View File

@ -168,6 +168,14 @@ class DBusCachedPlugin(val config : DataCacheConfig,
dBus.cmd << optionPipe(dBusCmdMasterPipe, cmdBuf)(_.m2sPipe()) dBus.cmd << optionPipe(dBusCmdMasterPipe, cmdBuf)(_.m2sPipe())
cache.io.mem.rsp << optionPipe(dBusRspSlavePipe,dBus.rsp)(_.m2sPipe()) cache.io.mem.rsp << optionPipe(dBusRspSlavePipe,dBus.rsp)(_.m2sPipe())
pipeline plug new Area{
//Memory bandwidth counter
val rspCounter = RegInit(UInt(32 bits)) init(0)
when(dBus.rsp.valid){
rspCounter := rspCounter + 1
}
}
decode plug new Area { decode plug new Area {
import decode._ import decode._

6
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
View File

@ -130,6 +130,12 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
iBus <> cache.io.mem iBus <> cache.io.mem
iBus.cmd.address.allowOverride := cache.io.mem.cmd.address iBus.cmd.address.allowOverride := cache.io.mem.cmd.address
//Memory bandwidth counter
val rspCounter = RegInit(UInt(32 bits)) init(0)
when(iBus.rsp.valid){
rspCounter := rspCounter + 1
}
val stageOffset = if(relaxedPcCalculation) 1 else 0 val stageOffset = if(relaxedPcCalculation) 1 else 0
def stages = iBusRsp.stages.drop(stageOffset) def stages = iBusRsp.stages.drop(stageOffset)