Add cache Bandwidth counter, previous commit was about random instruction cache way allocation
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94606d38e2
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4a40184b35
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@ -168,6 +168,14 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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dBus.cmd << optionPipe(dBusCmdMasterPipe, cmdBuf)(_.m2sPipe())
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dBus.cmd << optionPipe(dBusCmdMasterPipe, cmdBuf)(_.m2sPipe())
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cache.io.mem.rsp << optionPipe(dBusRspSlavePipe,dBus.rsp)(_.m2sPipe())
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cache.io.mem.rsp << optionPipe(dBusRspSlavePipe,dBus.rsp)(_.m2sPipe())
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pipeline plug new Area{
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//Memory bandwidth counter
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val rspCounter = RegInit(UInt(32 bits)) init(0)
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when(dBus.rsp.valid){
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rspCounter := rspCounter + 1
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}
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}
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decode plug new Area {
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decode plug new Area {
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import decode._
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import decode._
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@ -129,7 +129,13 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
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iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
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iBus <> cache.io.mem
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iBus <> cache.io.mem
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iBus.cmd.address.allowOverride := cache.io.mem.cmd.address
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iBus.cmd.address.allowOverride := cache.io.mem.cmd.address
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//Memory bandwidth counter
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val rspCounter = RegInit(UInt(32 bits)) init(0)
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when(iBus.rsp.valid){
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rspCounter := rspCounter + 1
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}
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val stageOffset = if(relaxedPcCalculation) 1 else 0
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val stageOffset = if(relaxedPcCalculation) 1 else 0
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def stages = iBusRsp.stages.drop(stageOffset)
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def stages = iBusRsp.stages.drop(stageOffset)
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