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Merge pull request #21 from tomverbeure/typos 

Typos...
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Dolu1990 2018-05-28 20:24:52 +02:00 committed by GitHub
parent 1752b5f184 0335543309
commit 4a433e16f1
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3 changed files with 16 additions and 16 deletions
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4
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -117,8 +117,8 @@ object TestsWorkspace {
new MulDivIterativePlugin( new MulDivIterativePlugin(
genMul = true, genMul = true,
genDiv = true, genDiv = true,
mulUnroolFactor = 32, mulUnrollFactor = 32,
divUnroolFactor = 1 divUnrollFactor = 1
), ),
// new DivPlugin, // new DivPlugin,
new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)), new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)),

2
src/main/scala/vexriscv/plugin/DivPlugin.scala
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@ -4,7 +4,7 @@ import vexriscv.{VexRiscv, _}
import spinal.core._ import spinal.core._
// DivPlugin was by the past a standalone plugin, but now it use the MulDivIterativePlugin implementation // DivPlugin was by the past a standalone plugin, but now it use the MulDivIterativePlugin implementation
class DivPlugin extends MulDivIterativePlugin(genMul = false, genDiv = true, mulUnroolFactor = 1, divUnroolFactor = 1) class DivPlugin extends MulDivIterativePlugin(genMul = false, genDiv = true, mulUnrollFactor = 1, divUnrollFactor = 1)
//import spinal.lib.math.MixedDivider //import spinal.lib.math.MixedDivider
// //

22
src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala
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@ -4,7 +4,7 @@ import spinal.core._
import spinal.lib._ import spinal.lib._
import vexriscv.{VexRiscv, _} import vexriscv.{VexRiscv, _}
class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnroolFactor : Int, divUnroolFactor : Int) extends Plugin[VexRiscv]{ class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnrollFactor : Int, divUnrollFactor : Int) extends Plugin[VexRiscv]{
object IS_MUL extends Stageable(Bool) object IS_MUL extends Stageable(Bool)
object IS_DIV extends Stageable(Bool) object IS_DIV extends Stageable(Bool)
object IS_REM extends Stageable(Bool) object IS_REM extends Stageable(Bool)
@ -68,17 +68,17 @@ class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnroolFactor
val mul = ifGen(genMul) (new Area{ val mul = ifGen(genMul) (new Area{
assert(isPow2(mulUnroolFactor)) assert(isPow2(mulUnrollFactor))
val counter = Counter(32 / mulUnroolFactor + 1) val counter = Counter(32 / mulUnrollFactor + 1)
val done = counter.willOverflowIfInc val done = counter.willOverflowIfInc
when(arbitration.isValid && input(IS_MUL)){ when(arbitration.isValid && input(IS_MUL)){
when(!done){ when(!done){
arbitration.haltItself := True arbitration.haltItself := True
counter.increment() counter.increment()
rs2 := rs2 |>> mulUnroolFactor rs2 := rs2 |>> mulUnrollFactor
val sumElements = ((0 until mulUnroolFactor).map(i => rs2(i) ? (rs1 << i) | U(0)) :+ (accumulator >> 32)) val sumElements = ((0 until mulUnrollFactor).map(i => rs2(i) ? (rs1 << i) | U(0)) :+ (accumulator >> 32))
val sumResult = sumElements.map(_.asSInt.resize(32 + mulUnroolFactor + 1).asUInt).reduceBalancedTree(_ + _) val sumResult = sumElements.map(_.asSInt.resize(32 + mulUnrollFactor + 1).asUInt).reduceBalancedTree(_ + _)
accumulator := (sumResult @@ accumulator(31 downto 0)) >> mulUnroolFactor accumulator := (sumResult @@ accumulator(31 downto 0)) >> mulUnrollFactor
} }
output(REGFILE_WRITE_DATA) := ((input(INSTRUCTION)(13 downto 12) === B"00") ? accumulator(31 downto 0) | accumulator(63 downto 32)).asBits output(REGFILE_WRITE_DATA) := ((input(INSTRUCTION)(13 downto 12) === B"00") ? accumulator(31 downto 0) | accumulator(63 downto 32)).asBits
} }
@ -86,7 +86,7 @@ class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnroolFactor
val div = ifGen(genDiv) (new Area{ val div = ifGen(genDiv) (new Area{
assert(isPow2(divUnroolFactor)) assert(isPow2(divUnrollFactor))
//register allocation //register allocation
def numerator = rs1(31 downto 0) def numerator = rs1(31 downto 0)
@ -94,7 +94,7 @@ class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnroolFactor
def remainder = accumulator(31 downto 0) def remainder = accumulator(31 downto 0)
val needRevert = Reg(Bool) val needRevert = Reg(Bool)
val counter = Counter(32 / divUnroolFactor + 2) val counter = Counter(32 / divUnrollFactor + 2)
val done = counter.willOverflowIfInc val done = counter.willOverflowIfInc
val result = Reg(Bits(32 bits)) val result = Reg(Bits(32 bits))
when(arbitration.isValid && input(IS_DIV)){ when(arbitration.isValid && input(IS_DIV)){
@ -116,9 +116,9 @@ class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnroolFactor
} }
} }
stages(numerator, remainder, divUnroolFactor) stages(numerator, remainder, divUnrollFactor)
when(counter === 32 / divUnroolFactor){ when(counter === 32 / divUnrollFactor){
val selectedResult = (input(INSTRUCTION)(13) ? remainder | numerator) val selectedResult = (input(INSTRUCTION)(13) ? remainder | numerator)
result := selectedResult.twoComplement(needRevert).asBits.resized result := selectedResult.twoComplement(needRevert).asBits.resized
} }