Removes PDF and xilinx-xc7.cfg and jtagspi.cfg. Enhances README.md to find in OpenOCD.

This commit is contained in:
Frank Poppen 2021-05-06 17:31:40 +02:00
parent 47110a97a3
commit 5a7c71259d
4 changed files with 1 additions and 103 deletions

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@ -104,7 +104,7 @@ in e.g. the path: `project_name.srcs\sources_1\imports\Downloads`
1. `usb_connect.cfg` (interface configuration) 1. `usb_connect.cfg` (interface configuration)
2. `soc_init.cfg` (take over the control of the CPU) 2. `soc_init.cfg` (take over the control of the CPU)
* `usb_connect.cfg` * `usb_connect.cfg`
You can take it from … https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/digilent/ArtyA7SmpLinux/openocd/usb_connect.cfg … without modifications as we would say, but make sure to check the entire path in your system for the files `xilinx-xc7.cfg` and `jtagspi.cfg`. If required, adapt the find and path for the lines: You can take it from ... https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/digilent/ArtyA7SmpLinux/openocd/usb_connect.cfg ... without modifications as we would say. Be aware that it includes the two files `xilinx-xc7.cfg` and `jtagspi.cfg` which are part of the OpenOCD project ... https://github.com/riscv/riscv-openocd/tree/riscv/tcl/cpld , but make sure to check the path for the files. If required, adapt the find and path for the lines:
``` ```
[29] source [find cpld/xilinx-xc7.cfg] [29] source [find cpld/xilinx-xc7.cfg]
[30] source [find cpld/jtagspi.cfg] [30] source [find cpld/jtagspi.cfg]

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@ -1,37 +0,0 @@
set _USER1 0x02
if { [info exists JTAGSPI_IR] } {
set _JTAGSPI_IR $JTAGSPI_IR
} else {
set _JTAGSPI_IR $_USER1
}
if { [info exists TARGETNAME] } {
set _TARGETNAME $TARGETNAME
} else {
set _TARGETNAME $_CHIPNAME.proxy
}
if { [info exists FLASHNAME] } {
set _FLASHNAME $FLASHNAME
} else {
set _FLASHNAME $_CHIPNAME.spi
}
target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
proc jtagspi_init {chain_id proxy_bit} {
# load proxy bitstream $proxy_bit and probe spi flash
global _FLASHNAME
pld load $chain_id $proxy_bit
reset halt
flash probe $_FLASHNAME
}
proc jtagspi_program {bin addr} {
# write and verify binary file $bin at offset $addr
global _FLASHNAME
flash write_image erase $bin $addr
flash verify_bank $_FLASHNAME $bin $addr
}

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@ -1,65 +0,0 @@
# xilinx series 7 (artix, kintex, virtex)
# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME xc7
}
# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
-expected-id 0x03622093 \
-expected-id 0x03620093 \
-expected-id 0x037C4093 \
-expected-id 0x0362F093 \
-expected-id 0x037C8093 \
-expected-id 0x037C7093 \
-expected-id 0x037C3093 \
-expected-id 0x0362E093 \
-expected-id 0x037C2093 \
-expected-id 0x0362D093 \
-expected-id 0x0362C093 \
-expected-id 0x03632093 \
-expected-id 0x03631093 \
-expected-id 0x03636093 \
-expected-id 0x03647093 \
-expected-id 0x0364C093 \
-expected-id 0x03651093 \
-expected-id 0x03747093 \
-expected-id 0x03656093 \
-expected-id 0x03752093 \
-expected-id 0x03751093 \
-expected-id 0x03671093 \
-expected-id 0x036B3093 \
-expected-id 0x036B7093 \
-expected-id 0x036BB093 \
-expected-id 0x036BF093 \
-expected-id 0x03667093 \
-expected-id 0x03682093 \
-expected-id 0x03687093 \
-expected-id 0x03692093 \
-expected-id 0x03691093 \
-expected-id 0x03696093 \
-expected-id 0x036D5093 \
-expected-id 0x036D9093 \
-expected-id 0x036DB093
pld device virtex2 $_CHIPNAME.tap 1
set XC7_JSHUTDOWN 0x0d
set XC7_JPROGRAM 0x0b
set XC7_JSTART 0x0c
set XC7_BYPASS 0x3f
proc xc7_program {tap} {
global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
irscan $tap $XC7_JSHUTDOWN
irscan $tap $XC7_JPROGRAM
runtest 60000
#JSTART prevents this from working...
#irscan $tap $XC7_JSTART
runtest 2000
irscan $tap $XC7_BYPASS
runtest 2000
}