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#170 wishbone example now set dBusCmdMasterPipe

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Dolu1990 2021-08-24 23:24:22 +02:00
parent 3deeab42fd
commit 5c7e4a0294
1 changed files with 1 additions and 0 deletions
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src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
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@ -64,6 +64,7 @@ object VexRiscvCachedWishboneForSim{
catchIllegal = true, catchIllegal = true,
catchUnaligned = true catchUnaligned = true
), ),
dBusCmdMasterPipe = true, //required for wishbone
memoryTranslatorPortConfig = null memoryTranslatorPortConfig = null
// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// portTlbSize = 6 // portTlbSize = 6