Fix relaxedPc/DYNAMIC_TARGET interaction

This commit is contained in:
Dolu1990 2018-06-06 18:30:30 +02:00
parent dc968020c4
commit 5e7dd02bf7
3 changed files with 23 additions and 8 deletions

View File

@ -33,12 +33,13 @@ object TestsWorkspace {
plugins = List( plugins = List(
new IBusSimplePlugin( new IBusSimplePlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
relaxedPcCalculation = false, relaxedPcCalculation = true,
relaxedBusCmdValid = false,
prediction = DYNAMIC_TARGET, prediction = DYNAMIC_TARGET,
historyRamSizeLog2 = 10, historyRamSizeLog2 = 10,
catchAccessFault = true, catchAccessFault = true,
compressedGen = true, compressedGen = false,
busLatencyMin = 3 busLatencyMin = 1
), ),
// new IBusCachedPlugin( // new IBusCachedPlugin(
// resetVector = 0x80000000l, // resetVector = 0x80000000l,

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@ -126,18 +126,21 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
} }
} }
preOutput.valid := RegNext(True) init (False) // && !jump.pcLoad.valid
preOutput.payload := pcReg
//application of the selected jump request //application of the selected jump request
if(predictionPcLoad != null) { if(predictionPcLoad != null) {
when(predictionPcLoad.valid) { when(predictionPcLoad.valid) {
pcReg := predictionPcLoad.payload pcReg := predictionPcLoad.payload
preOutput.valid := False
} }
} }
when(jump.pcLoad.valid) { when(jump.pcLoad.valid) {
pcReg := jump.pcLoad.payload pcReg := jump.pcLoad.payload
} }
preOutput.valid := RegNext(True) init (False) // && !jump.pcLoad.valid
preOutput.payload := pcReg
} else new PcFetch{ } else new PcFetch{
//PC calculation without Jump //PC calculation without Jump
val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public) val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public)

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@ -202,8 +202,8 @@ class IBusDimension extends VexRiscvDimension("IBus") {
busLatencyMin = latency, busLatencyMin = latency,
injectorStage = injectorStage injectorStage = injectorStage
) )
}) :+ new VexRiscvPosition("FullRelaxed"){ }) :+ new VexRiscvPosition("FullRelaxedDeep"){
override def testParam = "IBUS=SIMPLE" override def testParam = "IBUS=SIMPLE COMPRESSED=yes"
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin( override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
relaxedPcCalculation = true, relaxedPcCalculation = true,
@ -212,10 +212,21 @@ class IBusDimension extends VexRiscvDimension("IBus") {
catchAccessFault = false, catchAccessFault = false,
compressedGen = true, compressedGen = true,
busLatencyMin = 3, busLatencyMin = 3,
injectorStage = false
)
} :+ new VexRiscvPosition("FullRelaxedStd") {
override def testParam = "IBUS=SIMPLE"
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin(
resetVector = 0x80000000l,
relaxedPcCalculation = true,
relaxedBusCmdValid = true,
prediction = STATIC,
catchAccessFault = false,
compressedGen = false,
busLatencyMin = 1,
injectorStage = true injectorStage = true
) )
} }
} }