Fix DataCache atomic integration into DBusCachedPlugin
Atomic is passing basic tests
This commit is contained in:
Dolu1990
parent
4637e6cb48
commit
611f2f487f
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@ -15,6 +15,8 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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var privilegeService : PrivilegeService = null
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object MEMORY_ENABLE extends Stageable(Bool)
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object MEMORY_MANAGMENT extends Stageable(Bool)
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object MEMORY_WR extends Stageable(Bool)
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object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits))
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object MEMORY_ATOMIC extends Stageable(Bool)
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@ -35,12 +37,16 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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SRC2_CTRL -> Src2CtrlEnum.IMI,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> False,
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BYPASSABLE_MEMORY_STAGE -> False
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BYPASSABLE_MEMORY_STAGE -> False,
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MEMORY_WR -> False,
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MEMORY_MANAGMENT -> False
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)
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val storeActions = stdActions ++ List(
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SRC2_CTRL -> Src2CtrlEnum.IMS,
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RS2_USE -> True
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RS2_USE -> True,
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MEMORY_WR -> True,
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MEMORY_MANAGMENT -> False
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)
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decoderService.addDefault(MEMORY_ENABLE, False)
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@ -56,7 +62,6 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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decoderService.add(
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key = LR,
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values = loadActions.filter(_._1 != SRC2_CTRL) ++ Seq(
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RS2_USE -> True,
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SRC2_CTRL -> Src2CtrlEnum.RS,
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MEMORY_ATOMIC -> True
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)
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@ -64,7 +69,6 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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decoderService.add(
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key = SC,
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values = storeActions.filter(_._1 != SRC2_CTRL) ++ Seq(
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SRC2_CTRL -> Src2CtrlEnum.RS,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> False,
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BYPASSABLE_MEMORY_STAGE -> False,
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@ -76,7 +80,8 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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def MANAGEMENT = M"-------00000-----101-----0001111"
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decoderService.add(MANAGEMENT, stdActions ++ List(
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SRC2_CTRL -> Src2CtrlEnum.RS,
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RS2_USE -> True
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RS2_USE -> True,
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MEMORY_MANAGMENT -> True
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))
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mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(pipeline.memory,memoryTranslatorPortConfig)
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@ -119,13 +124,11 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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execute plug new Area {
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import execute._
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//TODO manage removeIt
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val size = input(INSTRUCTION)(13 downto 12).asUInt
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cache.io.cpu.execute.isValid := arbitration.isValid && input(MEMORY_ENABLE)
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cache.io.cpu.execute.isStuck := arbitration.isStuck
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// arbitration.haltIt.setWhen(cache.io.cpu.execute.haltIt)
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cache.io.cpu.execute.args.wr := input(INSTRUCTION)(5)
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cache.io.cpu.execute.args.wr := input(MEMORY_WR)
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cache.io.cpu.execute.args.address := input(SRC_ADD).asUInt
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cache.io.cpu.execute.args.data := size.mux(
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U(0) -> input(RS2)( 7 downto 0) ## input(RS2)( 7 downto 0) ## input(RS2)(7 downto 0) ## input(RS2)(7 downto 0),
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@ -134,11 +137,17 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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)
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cache.io.cpu.execute.args.size := size
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cache.io.cpu.execute.args.forceUncachedAccess := False
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cache.io.cpu.execute.args.kind := input(INSTRUCTION)(2) ? DataCacheCpuCmdKind.MANAGMENT | DataCacheCpuCmdKind.MEMORY
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cache.io.cpu.execute.args.kind := input(MEMORY_MANAGMENT) ? DataCacheCpuCmdKind.MANAGMENT | DataCacheCpuCmdKind.MEMORY
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cache.io.cpu.execute.args.clean := input(INSTRUCTION)(28)
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cache.io.cpu.execute.args.invalidate := input(INSTRUCTION)(29)
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cache.io.cpu.execute.args.way := input(INSTRUCTION)(30)
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if(genAtomic) cache.io.cpu.execute.args.isAtomic := input(MEMORY_ATOMIC)
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if(genAtomic) {
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cache.io.cpu.execute.args.isAtomic := False
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when(input(MEMORY_ATOMIC)){
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cache.io.cpu.execute.args.isAtomic := True
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cache.io.cpu.execute.args.address := input(SRC1).asUInt
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}
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}
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insert(MEMORY_ADDRESS_LOW) := cache.io.cpu.execute.args.address(1 downto 0)
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}
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@ -165,10 +174,10 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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exceptionBus.badAddr := cache.io.cpu.writeBack.badAddr
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exceptionBus.code.assignDontCare()
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when(cache.io.cpu.writeBack.illegalAccess || cache.io.cpu.writeBack.accessError){
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exceptionBus.code := (input(INSTRUCTION)(5) ? U(7) | U(5)).resized
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exceptionBus.code := (input(MEMORY_WR) ? U(7) | U(5)).resized
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}
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when(cache.io.cpu.writeBack.unalignedAccess){
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exceptionBus.code := (input(INSTRUCTION)(5) ? U(6) | U(4)).resized
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exceptionBus.code := (input(MEMORY_WR) ? U(6) | U(4)).resized
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}
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when(cache.io.cpu.writeBack.mmuMiss){
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exceptionBus.code := 13
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@ -10,35 +10,62 @@ Disassembly of section .crt_section:
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8: 06400593 li a1,100
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c: 06500613 li a2,101
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10: 06600693 li a3,102
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14: 00d52023 sw a3,0(a0) # 10000000 <pass+0xfffffa0>
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14: 00d52023 sw a3,0(a0) # 10000000 <pass+0xfffff34>
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18: 18b5262f sc.w a2,a1,(a0)
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1c: 02060c63 beqz a2,54 <fail>
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20: 00052703 lw a4,0(a0)
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24: 02e69863 bne a3,a4,54 <fail>
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28: 00200e13 li t3,2
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2c: 10000537 lui a0,0x10000
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30: 06400593 li a1,100
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34: 06500613 li a2,101
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38: 06600693 li a3,102
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3c: 00d52023 sw a3,0(a0) # 10000000 <pass+0xfffffa0>
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40: 18b5262f sc.w a2,a1,(a0)
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44: 00060863 beqz a2,54 <fail>
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48: 00052703 lw a4,0(a0)
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4c: 00e69463 bne a3,a4,54 <fail>
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50: 0100006f j 60 <pass>
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1c: 00100713 li a4,1
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20: 0ae61063 bne a2,a4,c0 <fail>
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24: 00052703 lw a4,0(a0)
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28: 08e69c63 bne a3,a4,c0 <fail>
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2c: 00200e13 li t3,2
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30: 10000537 lui a0,0x10000
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34: 00450513 addi a0,a0,4 # 10000004 <pass+0xfffff38>
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38: 06700593 li a1,103
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3c: 06800613 li a2,104
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40: 06900693 li a3,105
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44: 00d52023 sw a3,0(a0)
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48: 18b5262f sc.w a2,a1,(a0)
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4c: 00100713 li a4,1
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50: 06e61863 bne a2,a4,c0 <fail>
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54: 00052703 lw a4,0(a0)
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58: 06e69463 bne a3,a4,c0 <fail>
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5c: 00300e13 li t3,3
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60: 10000537 lui a0,0x10000
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64: 00450513 addi a0,a0,4 # 10000004 <pass+0xfffff38>
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68: 06700593 li a1,103
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6c: 06800613 li a2,104
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70: 06900693 li a3,105
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74: 18b5262f sc.w a2,a1,(a0)
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78: 00100713 li a4,1
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7c: 04e61263 bne a2,a4,c0 <fail>
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80: 00052703 lw a4,0(a0)
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84: 02e69e63 bne a3,a4,c0 <fail>
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88: 00400e13 li t3,4
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8c: 10000537 lui a0,0x10000
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90: 00850513 addi a0,a0,8 # 10000008 <pass+0xfffff3c>
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94: 06a00593 li a1,106
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98: 06b00613 li a2,107
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9c: 06c00693 li a3,108
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a0: 00d52023 sw a3,0(a0)
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a4: 100527af lr.w a5,(a0)
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a8: 18b5262f sc.w a2,a1,(a0)
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ac: 00d79a63 bne a5,a3,c0 <fail>
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b0: 00061863 bnez a2,c0 <fail>
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b4: 00052703 lw a4,0(a0)
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b8: 00e59463 bne a1,a4,c0 <fail>
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bc: 0100006f j cc <pass>
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00000054 <fail>:
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54: f0100137 lui sp,0xf0100
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58: f2410113 addi sp,sp,-220 # f00fff24 <pass+0xf00ffec4>
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5c: 01c12023 sw t3,0(sp)
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000000c0 <fail>:
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c0: f0100137 lui sp,0xf0100
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c4: f2410113 addi sp,sp,-220 # f00fff24 <pass+0xf00ffe58>
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c8: 01c12023 sw t3,0(sp)
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00000060 <pass>:
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60: f0100137 lui sp,0xf0100
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64: f2010113 addi sp,sp,-224 # f00fff20 <pass+0xf00ffec0>
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68: 00012023 sw zero,0(sp)
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6c: 00000013 nop
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70: 00000013 nop
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74: 00000013 nop
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78: 00000013 nop
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7c: 00000013 nop
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80: 00000013 nop
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000000cc <pass>:
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cc: f0100137 lui sp,0xf0100
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d0: f2010113 addi sp,sp,-224 # f00fff20 <pass+0xf00ffe54>
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d4: 00012023 sw zero,0(sp)
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d8: 00000013 nop
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dc: 00000013 nop
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e0: 00000013 nop
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e4: 00000013 nop
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e8: 00000013 nop
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ec: 00000013 nop
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Binary file not shown.
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@ -1,10 +1,16 @@
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:10000000130E100037050010930540061306500626
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:10001000930660062320D5002F26B518630C060230
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:10002000032705006398E602130E20003705001031
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:100030009305400613065006930660062320D5005C
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:100040002F26B51863080600032705006394E60011
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:100050006F000001370110F0130141F22320C101AC
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:10006000370110F0130101F22320010013000000FA
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:100070001300000013000000130000001300000034
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:040080001300000069
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:10001000930660062320D5002F26B518130710007D
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:100020006310E60A03270500639CE608130E200010
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:10003000370500101305450093057006130680066A
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:10004000930690062320D5002F26B518130710001D
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:100050006318E606032705006394E606130E3000D6
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:10006000370500101305450093057006130680063A
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:10007000930690062F26B518130710006312E604A6
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:1000800003270500639EE602130E400037050010AB
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:10009000130585009305A0061306B0069306C00657
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:1000A0002320D500AF2705102F26B518639AD70057
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:1000B00063180600032705006394E5006F00000144
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:1000C000370110F0130141F22320C101370110F074
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:1000D000130101F2232001001300000013000000AF
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:1000E00013000000130000001300000013000000C4
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:00000001FF
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@ -16,15 +16,15 @@ END GROUP
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a
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0x0000000000000000 . = 0x0
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.crt_section 0x0000000000000000 0x84
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.crt_section 0x0000000000000000 0xf0
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0x0000000000000000 . = ALIGN (0x4)
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*crt.o(.text)
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.text 0x0000000000000000 0x84 build/src/crt.o
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.text 0x0000000000000000 0xf0 build/src/crt.o
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0x0000000000000000 _start
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OUTPUT(build/atomic.elf elf32-littleriscv)
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.data 0x0000000000000084 0x0
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.data 0x0000000000000084 0x0 build/src/crt.o
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.data 0x00000000000000f0 0x0
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.data 0x00000000000000f0 0x0 build/src/crt.o
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.bss 0x0000000000000084 0x0
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.bss 0x0000000000000084 0x0 build/src/crt.o
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.bss 0x00000000000000f0 0x0
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.bss 0x00000000000000f0 0x0 build/src/crt.o
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@ -1,10 +1,16 @@
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@00000000
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13 0E 10 00 37 05 00 10 93 05 40 06 13 06 50 06
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93 06 60 06 23 20 D5 00 2F 26 B5 18 63 0C 06 02
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03 27 05 00 63 98 E6 02 13 0E 20 00 37 05 00 10
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93 05 40 06 13 06 50 06 93 06 60 06 23 20 D5 00
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2F 26 B5 18 63 08 06 00 03 27 05 00 63 94 E6 00
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6F 00 00 01 37 01 10 F0 13 01 41 F2 23 20 C1 01
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37 01 10 F0 13 01 01 F2 23 20 01 00 13 00 00 00
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93 06 60 06 23 20 D5 00 2F 26 B5 18 13 07 10 00
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63 10 E6 0A 03 27 05 00 63 9C E6 08 13 0E 20 00
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37 05 00 10 13 05 45 00 93 05 70 06 13 06 80 06
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93 06 90 06 23 20 D5 00 2F 26 B5 18 13 07 10 00
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63 18 E6 06 03 27 05 00 63 94 E6 06 13 0E 30 00
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37 05 00 10 13 05 45 00 93 05 70 06 13 06 80 06
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93 06 90 06 2F 26 B5 18 13 07 10 00 63 12 E6 04
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03 27 05 00 63 9E E6 02 13 0E 40 00 37 05 00 10
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13 05 85 00 93 05 A0 06 13 06 B0 06 93 06 C0 06
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23 20 D5 00 AF 27 05 10 2F 26 B5 18 63 9A D7 00
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63 18 06 00 03 27 05 00 63 94 E5 00 6F 00 00 01
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37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0
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13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00
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13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
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13 00 00 00
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@ -10,23 +10,51 @@ _start:
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li a3, 102
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sw a3, 0(a0)
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sc.w a2, a1, (a0)
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beq a2, x0, fail
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li a4, 1
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bne a2, a4, fail
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lw a4, 0(a0)
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bne a3, a4, fail
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//Test 2 retrying SC on unreserved area should fail and not write memory
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//Test 2 SC on another unreserved area should fail and not write memory
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li x28, 2
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li a0, 0x10000000
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li a1, 100
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li a2, 101
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li a3, 102
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li a0, 0x10000004
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li a1, 103
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li a2, 104
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li a3, 105
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sw a3, 0(a0)
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sc.w a2, a1, (a0)
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beq a2, x0, fail
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li a4, 1
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bne a2, a4, fail
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lw a4, 0(a0)
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bne a3, a4, fail
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//Test 3 retrying SC on unreserved area should fail and not write memory
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li x28, 3
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li a0, 0x10000004
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li a1, 103
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li a2, 104
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li a3, 105
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sc.w a2, a1, (a0)
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li a4, 1
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bne a2, a4, fail
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lw a4, 0(a0)
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bne a3, a4, fail
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//Test 4 SC on reserved area should pass and should be written write memory
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li x28, 4
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li a0, 0x10000008
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li a1, 106
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li a2, 107
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li a3, 108
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sw a3, 0(a0)
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lr.w a5, (a0)
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sc.w a2, a1, (a0)
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bne a5, a3, fail
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bne a2, x0, fail
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lw a4, 0(a0)
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bne a1, a4, fail
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j pass
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