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csrPlugin : avoid using ALU to get SRC1 (which was useless)

This commit is contained in:
Dolu1990 2018-11-03 11:29:30 +01:00
parent 978232fd63
commit 662d76e3aa
1 changed files with 2 additions and 3 deletions
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5
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -282,8 +282,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
val defaultCsrActions = List[(Stageable[_ <: BaseType],Any)]( val defaultCsrActions = List[(Stageable[_ <: BaseType],Any)](
IS_CSR -> True, IS_CSR -> True,
REGFILE_WRITE_VALID -> True, REGFILE_WRITE_VALID -> True,
ALU_BITWISE_CTRL -> AluBitwiseCtrlEnum.SRC1, BYPASSABLE_MEMORY_STAGE -> True
ALU_CTRL -> AluCtrlEnum.BITWISE
) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil) ) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil)
val nonImmediatActions = defaultCsrActions ++ List( val nonImmediatActions = defaultCsrActions ++ List(
@ -786,7 +785,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
val imm = IMM(input(INSTRUCTION)) val imm = IMM(input(INSTRUCTION))
val writeSrc = input(REGFILE_WRITE_DATA) val writeSrc = input(SRC1)
val readData = B(0, 32 bits) val readData = B(0, 32 bits)
// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT // def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT
// val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) // val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck)