Better cache invalidation doc
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@ -1038,7 +1038,7 @@ There is at least one cycle latency between a cmd and the corresponding rsp. The
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Multi way cache implementation with writh-through and allocate on read strategy. (Documentation is WIP)
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You can invalidate the whole cache via the 0x500F instruction, and you can invalidate a address range of one line via the instruction 0x500F | RS1 << 15 where RS1 should not be X0.
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You can invalidate the whole cache via the 0x500F instruction, and you can invalidate a address range (single line size) via the instruction 0x500F | RS1 << 15 where RS1 should not be X0 and point to one byte of the desired address to invalidate.
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#### MulPlugin
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