mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
Merge branch 'dev'
This commit is contained in:
Dolu1990
commit
77e361e91e
12 changed files with 97 additions and 85 deletions
2
.github/workflows/scala.yml
vendored
2
.github/workflows/scala.yml
vendored
|
|
@ -40,7 +40,7 @@ jobs:
|
|||
with:
|
||||
path: |
|
||||
~/tools
|
||||
key: ${{ runner.os }}-tools_v2
|
||||
key: ${{ runner.os }}-tools_v4
|
||||
|
||||
- name: Setup env
|
||||
run: echo "$HOME/tools/bin" >> $GITHUB_PATH
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@ unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
|
|||
unset VERILATOR_ROOT # For bash
|
||||
cd verilator
|
||||
git pull # Make sure we're up-to-date
|
||||
git checkout v4.040
|
||||
git checkout v4.216
|
||||
autoconf # Create ./configure script
|
||||
./configure
|
||||
make
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
val spinalVersion = "1.6.1"
|
||||
val spinalVersion = "1.6.2"
|
||||
|
||||
lazy val root = (project in file(".")).
|
||||
settings(
|
||||
|
|
@ -17,4 +17,4 @@ lazy val root = (project in file(".")).
|
|||
name := "VexRiscv"
|
||||
)
|
||||
|
||||
fork := true
|
||||
fork := true
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
|
|||
|
||||
withDebug.get match {
|
||||
case DEBUG_JTAG => jtag <> plugin.io.bus.fromJtag()
|
||||
case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain)
|
||||
case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain, 0)
|
||||
case DEBUG_BUS => debugBus <> plugin.io.bus
|
||||
case DEBUG_BMB => debugBmb >> plugin.io.bus.fromBmb()
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ import spinal.lib.generator._
|
|||
import vexriscv.ip.fpu.FpuParameter
|
||||
|
||||
case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig],
|
||||
jtagHeaderIgnoreWidth : Int,
|
||||
withExclusiveAndInvalidation : Boolean,
|
||||
forcePeripheralWidth : Boolean = true,
|
||||
outOfOrderDecoder : Boolean = true,
|
||||
|
|
@ -51,7 +52,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
|
|||
|
||||
implicit val interconnect = BmbInterconnectGenerator()
|
||||
|
||||
val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator()
|
||||
val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator(p.jtagHeaderIgnoreWidth)
|
||||
debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))
|
||||
|
||||
val debugPort = Handle(debugBridge.logic.jtagBridge.io.ctrl.toIo)
|
||||
|
|
|
|||
|
|
@ -175,7 +175,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
|
|||
withExclusiveAndInvalidation = coherency,
|
||||
forcePeripheralWidth = !wishboneMemory,
|
||||
outOfOrderDecoder = outOfOrderDecoder,
|
||||
fpu = fpu
|
||||
fpu = fpu,
|
||||
jtagHeaderIgnoreWidth = 0
|
||||
),
|
||||
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
|
||||
liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
|
||||
|
|
@ -250,7 +251,8 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
|
|||
resetVector = 0x80000000l
|
||||
)
|
||||
},
|
||||
withExclusiveAndInvalidation = true
|
||||
withExclusiveAndInvalidation = true,
|
||||
jtagHeaderIgnoreWidth = 0
|
||||
),
|
||||
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
|
||||
liteDramMapping = SizeMapping(0x80000000l, 0x70000000l),
|
||||
|
|
|
|||
|
|
@ -175,6 +175,7 @@ case class FenceFlags() extends Bundle {
|
|||
case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMasterSlave{
|
||||
val isValid = Bool()
|
||||
val isStuck = Bool()
|
||||
val isFiring = Bool()
|
||||
val isUser = Bool()
|
||||
val haltIt = Bool()
|
||||
val isWrite = Bool()
|
||||
|
|
@ -187,7 +188,7 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
|
|||
val exclusiveOk = Bool()
|
||||
|
||||
override def asMaster(): Unit = {
|
||||
out(isValid,isStuck,isUser, address, fence, storeData)
|
||||
out(isValid,isStuck,isUser, address, fence, storeData, isFiring)
|
||||
in(haltIt, data, mmuException, unalignedAccess, accessError, isWrite, keepMemRspData, exclusiveOk)
|
||||
}
|
||||
}
|
||||
|
|
@ -864,8 +865,9 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
|
|||
|
||||
val lrSc = withInternalLrSc generate new Area{
|
||||
val reserved = RegInit(False)
|
||||
when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.isLrsc){
|
||||
reserved := !request.wr
|
||||
when(io.cpu.writeBack.isValid && io.cpu.writeBack.isFiring){
|
||||
reserved setWhen(request.isLrsc)
|
||||
reserved clearWhen(request.wr)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1167,4 +1169,4 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
|
|||
s1.invalidations := RegNextWhen((input.valid && input.enable && input.address(lineRange) === s0.input.address(lineRange)) ? wayHits | 0, s0.input.ready)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -395,6 +395,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
|
|||
import managementStage._
|
||||
cache.io.cpu.writeBack.isValid := arbitration.isValid && input(MEMORY_ENABLE)
|
||||
cache.io.cpu.writeBack.isStuck := arbitration.isStuck
|
||||
cache.io.cpu.writeBack.isFiring := arbitration.isFiring
|
||||
cache.io.cpu.writeBack.isUser := (if(privilegeService != null) privilegeService.isUser() else False)
|
||||
cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA))
|
||||
cache.io.cpu.writeBack.storeData.subdivideIn(32 bits).foreach(_ := input(MEMORY_STORE_DATA_RF))
|
||||
|
|
|
|||
|
|
@ -462,8 +462,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
|
|||
val atomic = withLrSc generate new Area{
|
||||
val reserved = RegInit(False)
|
||||
insert(ATOMIC_HIT) := reserved
|
||||
when(arbitration.isFiring && input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){
|
||||
reserved := !input(MEMORY_STORE)
|
||||
when(arbitration.isFiring && input(MEMORY_ENABLE) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){
|
||||
reserved setWhen(input(MEMORY_ATOMIC))
|
||||
reserved clearWhen(input(MEMORY_STORE))
|
||||
}
|
||||
when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){
|
||||
skipCmd := True
|
||||
|
|
@ -566,8 +567,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
|
|||
}
|
||||
}
|
||||
|
||||
if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage)
|
||||
assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend")
|
||||
// if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage)
|
||||
// assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend")
|
||||
|
||||
//formal
|
||||
insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA)
|
||||
|
|
|
|||
|
|
@ -137,13 +137,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
|
|||
jtagBridge.io.jtag
|
||||
}
|
||||
|
||||
def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain): JtagTapInstructionCtrl ={
|
||||
def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain, jtagHeaderIgnoreWidth : Int): JtagTapInstructionCtrl ={
|
||||
val jtagConfig = SystemDebuggerConfig(
|
||||
memAddressWidth = 32,
|
||||
memDataWidth = 32,
|
||||
remoteCmdWidth = 1
|
||||
)
|
||||
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
|
||||
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth)
|
||||
val debugger = new SystemDebugger(jtagConfig)
|
||||
debugger.io.remote <> jtagBridge.io.remote
|
||||
debugger.io.mem <> this.from(jtagConfig)
|
||||
|
|
@ -151,13 +151,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
|
|||
jtagBridge.io.ctrl
|
||||
}
|
||||
|
||||
def fromBscane2(usedId : Int): Unit ={
|
||||
def fromBscane2(usedId : Int, jtagHeaderIgnoreWidth : Int): Unit ={
|
||||
val jtagConfig = SystemDebuggerConfig()
|
||||
|
||||
val bscane2 = BSCANE2(usedId)
|
||||
val jtagClockDomain = ClockDomain(bscane2.TCK)
|
||||
|
||||
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
|
||||
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth)
|
||||
jtagBridge.io.ctrl << bscane2.toJtagTapInstructionCtrl()
|
||||
|
||||
val debugger = new SystemDebugger(jtagConfig)
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
#include <time.h>
|
||||
#include "encoding.h"
|
||||
|
||||
#define VL_RANDOM_I_WIDTH(w) (VL_RANDOM_I() & (1l << w)-1l)
|
||||
|
||||
using namespace std;
|
||||
|
||||
struct timespec timer_get(){
|
||||
|
|
@ -897,6 +899,7 @@ public:
|
|||
dWrite(pAddr, size, (uint8_t*) &rsp.value);
|
||||
status.fs = 3;
|
||||
pcWrite(pc + 4);
|
||||
lrscReserved = false;
|
||||
}
|
||||
} break;
|
||||
#endif
|
||||
|
|
@ -948,6 +951,7 @@ public:
|
|||
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
|
||||
dWrite(pAddr, size, (uint8_t*)&i32_rs2);
|
||||
pcWrite(pc + 4);
|
||||
lrscReserved = false;
|
||||
}
|
||||
}break;
|
||||
case 0x13: //ALUi
|
||||
|
|
@ -1107,9 +1111,8 @@ public:
|
|||
int32_t src = i32_rs2;
|
||||
int32_t readValue;
|
||||
|
||||
#ifdef DBUS_EXCLUSIVE
|
||||
lrscReserved = false;
|
||||
#endif
|
||||
|
||||
|
||||
uint32_t pAddr;
|
||||
if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; }
|
||||
|
|
@ -1178,6 +1181,7 @@ public:
|
|||
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
|
||||
dWrite(pAddr, 4, (uint8_t*)&i16_rf2);
|
||||
pcWrite(pc + 2);
|
||||
lrscReserved = false;
|
||||
}
|
||||
}break;
|
||||
case 8: rfWrite(rd32, regs[rd32] + i16_imm); pcWrite(pc + 2); break;
|
||||
|
|
@ -1243,6 +1247,7 @@ public:
|
|||
} else {
|
||||
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
|
||||
dWrite(pAddr, 4, (uint8_t*)®s[iBits(2,5)]); pcWrite(pc + 2);
|
||||
lrscReserved = false;
|
||||
}
|
||||
}break;
|
||||
}
|
||||
|
|
@ -1437,7 +1442,7 @@ public:
|
|||
}
|
||||
Workspace(string name){
|
||||
vcdName = name;
|
||||
//seed = VL_RANDOM_I(32)^VL_RANDOM_I(32)^0x1093472;
|
||||
//seed = VL_RANDOM_I_WIDTH(32)^VL_RANDOM_I_WIDTH(32)^0x1093472;
|
||||
//srand48(seed);
|
||||
// setIStall(false);
|
||||
// setDStall(false);
|
||||
|
|
@ -1850,9 +1855,9 @@ public:
|
|||
|
||||
for(SimElement* simElement : simElements) simElement->postCycle();
|
||||
#ifdef RVF
|
||||
top->fpuCmdHalt = VL_RANDOM_I(1);
|
||||
top->fpuCommitHalt = VL_RANDOM_I(1);
|
||||
top->fpuRspHalt = VL_RANDOM_I(1);
|
||||
top->fpuCmdHalt = VL_RANDOM_I_WIDTH(1);
|
||||
top->fpuCommitHalt = VL_RANDOM_I_WIDTH(1);
|
||||
top->fpuRspHalt = VL_RANDOM_I_WIDTH(1);
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -2049,7 +2054,7 @@ public:
|
|||
//TODO doesn't catch when instruction removed ?
|
||||
virtual void postCycle(){
|
||||
top->iBus_rsp_valid = 0;
|
||||
if(rPtr != wPtr && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
if(rPtr != wPtr && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
uint32_t inst_next;
|
||||
bool error_next;
|
||||
ws->iBusAccess(pendings[rPtr], &inst_next,&error_next);
|
||||
|
|
@ -2058,10 +2063,10 @@ public:
|
|||
top->iBus_rsp_valid = 1;
|
||||
top->iBus_rsp_payload_error = error_next;
|
||||
} else {
|
||||
top->iBus_rsp_payload_inst = VL_RANDOM_I(32);
|
||||
top->iBus_rsp_payload_error = VL_RANDOM_I(1);
|
||||
top->iBus_rsp_payload_inst = VL_RANDOM_I_WIDTH(32);
|
||||
top->iBus_rsp_payload_error = VL_RANDOM_I_WIDTH(1);
|
||||
}
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100;
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I_WIDTH(7) < 100;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -2136,18 +2141,18 @@ public:
|
|||
}
|
||||
//TODO doesn't catch when instruction removed ?
|
||||
virtual void postCycle(){
|
||||
if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
IBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop();
|
||||
top->iBusAvalon_readDataValid = 1;
|
||||
top->iBusAvalon_readData = rsp.data;
|
||||
top->iBusAvalon_response = rsp.error ? 3 : 0;
|
||||
} else {
|
||||
top->iBusAvalon_readDataValid = 0;
|
||||
top->iBusAvalon_readData = VL_RANDOM_I(32);
|
||||
top->iBusAvalon_response = VL_RANDOM_I(2);
|
||||
top->iBusAvalon_readData = VL_RANDOM_I_WIDTH(32);
|
||||
top->iBusAvalon_response = VL_RANDOM_I_WIDTH(2);
|
||||
}
|
||||
if(ws->iStall)
|
||||
top->iBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100;
|
||||
top->iBusAvalon_waitRequestn = VL_RANDOM_I_WIDTH(7) < 100;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -2184,15 +2189,15 @@ public:
|
|||
|
||||
virtual void postCycle(){
|
||||
if(ws->iStall)
|
||||
top->iBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I(7) < 100);
|
||||
top->iBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100);
|
||||
|
||||
if(pending && top->iBusAhbLite3_HREADY){
|
||||
top->iBusAhbLite3_HRDATA = iBusAhbLite3_HRDATA;
|
||||
top->iBusAhbLite3_HRESP = iBusAhbLite3_HRESP;
|
||||
pending = false;
|
||||
} else {
|
||||
top->iBusAhbLite3_HRDATA = VL_RANDOM_I(32);
|
||||
top->iBusAhbLite3_HRESP = VL_RANDOM_I(1);
|
||||
top->iBusAhbLite3_HRDATA = VL_RANDOM_I_WIDTH(32);
|
||||
top->iBusAhbLite3_HRESP = VL_RANDOM_I_WIDTH(1);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
@ -2230,7 +2235,7 @@ public:
|
|||
virtual void postCycle(){
|
||||
bool error;
|
||||
top->iBus_rsp_valid = 0;
|
||||
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
#ifdef IBUS_TC
|
||||
if((address & 0x70000000) == 0){
|
||||
printf("IBUS_CACHED access out of range\n");
|
||||
|
|
@ -2248,7 +2253,7 @@ public:
|
|||
address = address + IBUS_DATA_WIDTH/8;
|
||||
top->iBus_rsp_valid = 1;
|
||||
}
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100 && pendingCount == 0;
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I_WIDTH(7) < 100 && pendingCount == 0;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -2263,7 +2268,7 @@ struct IBusCachedAvalonTask{
|
|||
|
||||
class IBusCachedAvalon : public SimElement{
|
||||
public:
|
||||
uint32_t inst_next = VL_RANDOM_I(32);
|
||||
uint32_t inst_next = VL_RANDOM_I_WIDTH(32);
|
||||
bool error_next = false;
|
||||
|
||||
queue<IBusCachedAvalonTask> tasks;
|
||||
|
|
@ -2293,7 +2298,7 @@ public:
|
|||
virtual void postCycle(){
|
||||
bool error;
|
||||
top->iBusAvalon_readDataValid = 0;
|
||||
if(!tasks.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
if(!tasks.empty() && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
uint32_t &address = tasks.front().address;
|
||||
uint32_t &pendingCount = tasks.front().pendingCount;
|
||||
bool error;
|
||||
|
|
@ -2306,7 +2311,7 @@ public:
|
|||
tasks.pop();
|
||||
}
|
||||
if(ws->iStall)
|
||||
top->iBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100;
|
||||
top->iBusAvalon_waitRequestn = VL_RANDOM_I_WIDTH(7) < 100;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -2338,9 +2343,9 @@ public:
|
|||
virtual void postCycle(){
|
||||
|
||||
if(ws->iStall)
|
||||
top->iBusWishbone_ACK = VL_RANDOM_I(7) < 100;
|
||||
top->iBusWishbone_ACK = VL_RANDOM_I_WIDTH(7) < 100;
|
||||
|
||||
top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32);
|
||||
top->iBusWishbone_DAT_MISO = VL_RANDOM_I_WIDTH(32);
|
||||
if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) {
|
||||
if(top->iBusWishbone_WE){
|
||||
|
||||
|
|
@ -2358,7 +2363,7 @@ public:
|
|||
#ifdef DBUS_SIMPLE
|
||||
class DBusSimple : public SimElement{
|
||||
public:
|
||||
uint32_t data_next = VL_RANDOM_I(32);
|
||||
uint32_t data_next = VL_RANDOM_I_WIDTH(32);
|
||||
bool error_next = false;
|
||||
bool pending = false;
|
||||
|
||||
|
|
@ -2384,16 +2389,16 @@ public:
|
|||
|
||||
virtual void postCycle(){
|
||||
top->dBus_rsp_ready = 0;
|
||||
if(pending && (!ws->dStall || VL_RANDOM_I(7) < 100)){
|
||||
if(pending && (!ws->dStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
pending = false;
|
||||
top->dBus_rsp_ready = 1;
|
||||
top->dBus_rsp_data = data_next;
|
||||
top->dBus_rsp_error = error_next;
|
||||
} else{
|
||||
top->dBus_rsp_data = VL_RANDOM_I(32);
|
||||
top->dBus_rsp_data = VL_RANDOM_I_WIDTH(32);
|
||||
}
|
||||
|
||||
if(ws->dStall) top->dBus_cmd_ready = VL_RANDOM_I(7) < 100 && !pending;
|
||||
if(ws->dStall) top->dBus_cmd_ready = VL_RANDOM_I_WIDTH(7) < 100 && !pending;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -2435,18 +2440,18 @@ public:
|
|||
}
|
||||
//TODO doesn't catch when instruction removed ?
|
||||
virtual void postCycle(){
|
||||
if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
DBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop();
|
||||
top->dBusAvalon_readDataValid = 1;
|
||||
top->dBusAvalon_readData = rsp.data;
|
||||
top->dBusAvalon_response = rsp.error ? 3 : 0;
|
||||
} else {
|
||||
top->dBusAvalon_readDataValid = 0;
|
||||
top->dBusAvalon_readData = VL_RANDOM_I(32);
|
||||
top->dBusAvalon_response = VL_RANDOM_I(2);
|
||||
top->dBusAvalon_readData = VL_RANDOM_I_WIDTH(32);
|
||||
top->dBusAvalon_response = VL_RANDOM_I_WIDTH(2);
|
||||
}
|
||||
if(ws->iStall)
|
||||
top->dBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100;
|
||||
top->dBusAvalon_waitRequestn = VL_RANDOM_I_WIDTH(7) < 100;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -2489,10 +2494,10 @@ public:
|
|||
|
||||
virtual void postCycle(){
|
||||
if(ws->iStall)
|
||||
top->dBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I(7) < 100);
|
||||
top->dBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100);
|
||||
|
||||
top->dBusAhbLite3_HRDATA = VL_RANDOM_I(32);
|
||||
top->dBusAhbLite3_HRESP = VL_RANDOM_I(1);
|
||||
top->dBusAhbLite3_HRDATA = VL_RANDOM_I_WIDTH(32);
|
||||
top->dBusAhbLite3_HRESP = VL_RANDOM_I_WIDTH(1);
|
||||
|
||||
if(top->dBusAhbLite3_HREADY && dBusAhbLite3_HTRANS == 2 && !dBusAhbLite3_HWRITE){
|
||||
|
||||
|
|
@ -2531,8 +2536,8 @@ public:
|
|||
|
||||
virtual void postCycle(){
|
||||
if(ws->iStall)
|
||||
top->dBusWishbone_ACK = VL_RANDOM_I(7) < 100;
|
||||
top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32);
|
||||
top->dBusWishbone_ACK = VL_RANDOM_I_WIDTH(7) < 100;
|
||||
top->dBusWishbone_DAT_MISO = VL_RANDOM_I_WIDTH(32);
|
||||
if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) {
|
||||
if(top->dBusWishbone_WE){
|
||||
bool dummy;
|
||||
|
|
@ -2610,7 +2615,6 @@ public:
|
|||
bool hit = reservationValid && reservationAddress == top->dBus_cmd_payload_address;
|
||||
rsp.exclusive = hit;
|
||||
cancel = !hit;
|
||||
reservationValid = false;
|
||||
}
|
||||
if(!cancel) {
|
||||
for(int idx = 0;idx < 1;idx++){
|
||||
|
|
@ -2621,6 +2625,7 @@ public:
|
|||
}
|
||||
}
|
||||
|
||||
reservationValid = false;
|
||||
rsp.last = true;
|
||||
rsp.error = error;
|
||||
rsps.push(rsp);
|
||||
|
|
@ -2635,7 +2640,7 @@ public:
|
|||
ws->dBusAccess(top->dBus_cmd_payload_address,0,1 << top->dBus_cmd_payload_size,buffer, &error);
|
||||
for(int beat = 0;beat <= beatCount;beat++){
|
||||
for(int i = 0;i < DBUS_LOAD_DATA_WIDTH/8;i++){
|
||||
rsp.data[i] = (address >= startAt && address < endAt) ? buffer[address-top->dBus_cmd_payload_address] : VL_RANDOM_I(8);
|
||||
rsp.data[i] = (address >= startAt && address < endAt) ? buffer[address-top->dBus_cmd_payload_address] : VL_RANDOM_I_WIDTH(8);
|
||||
address += 1;
|
||||
}
|
||||
rsp.last = beat == beatCount;
|
||||
|
|
@ -2652,8 +2657,8 @@ public:
|
|||
|
||||
#ifdef DBUS_INVALIDATE
|
||||
if(ws->allowInvalidate){
|
||||
if(VL_RANDOM_I(7) < 10){
|
||||
invalidationHint.push(top->dBus_cmd_payload_address + VL_RANDOM_I(5));
|
||||
if(VL_RANDOM_I_WIDTH(7) < 10){
|
||||
invalidationHint.push(top->dBus_cmd_payload_address + VL_RANDOM_I_WIDTH(5));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2668,7 +2673,7 @@ public:
|
|||
|
||||
virtual void postCycle(){
|
||||
|
||||
if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I(7) < 100)){
|
||||
if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
DBusCachedTask rsp = rsps.front();
|
||||
rsps.pop();
|
||||
top->dBus_rsp_valid = 1;
|
||||
|
|
@ -2683,33 +2688,33 @@ public:
|
|||
} else{
|
||||
top->dBus_rsp_valid = 0;
|
||||
for(int idx = 0;idx < DBUS_LOAD_DATA_WIDTH/32;idx++){
|
||||
((uint32_t*)&top->dBus_rsp_payload_data)[idx] = VL_RANDOM_I(32);
|
||||
((uint32_t*)&top->dBus_rsp_payload_data)[idx] = VL_RANDOM_I_WIDTH(32);
|
||||
}
|
||||
top->dBus_rsp_payload_error = VL_RANDOM_I(1);
|
||||
top->dBus_rsp_payload_last = VL_RANDOM_I(1);
|
||||
top->dBus_rsp_payload_error = VL_RANDOM_I_WIDTH(1);
|
||||
top->dBus_rsp_payload_last = VL_RANDOM_I_WIDTH(1);
|
||||
#ifdef DBUS_EXCLUSIVE
|
||||
top->dBus_rsp_payload_exclusive = VL_RANDOM_I(1);
|
||||
top->dBus_rsp_payload_exclusive = VL_RANDOM_I_WIDTH(1);
|
||||
#endif
|
||||
}
|
||||
top->dBus_cmd_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1);
|
||||
top->dBus_cmd_ready = (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 100 : 1);
|
||||
|
||||
#ifdef DBUS_INVALIDATE
|
||||
if(ws->allowInvalidate){
|
||||
if(top->dBus_inv_ready) top->dBus_inv_valid = 0;
|
||||
if(top->dBus_inv_valid == 0 && VL_RANDOM_I(7) < 5){
|
||||
if(top->dBus_inv_valid == 0 && VL_RANDOM_I_WIDTH(7) < 5){
|
||||
top->dBus_inv_valid = 1;
|
||||
top->dBus_inv_payload_fragment_enable = VL_RANDOM_I(7) < 100;
|
||||
top->dBus_inv_payload_fragment_enable = VL_RANDOM_I_WIDTH(7) < 100;
|
||||
if(!invalidationHint.empty()){
|
||||
top->dBus_inv_payload_fragment_address = invalidationHint.front();
|
||||
invalidationHint.pop();
|
||||
} else {
|
||||
top->dBus_inv_payload_fragment_address = VL_RANDOM_I(32);
|
||||
top->dBus_inv_payload_fragment_address = VL_RANDOM_I_WIDTH(32);
|
||||
}
|
||||
}
|
||||
}
|
||||
top->dBus_ack_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1);
|
||||
top->dBus_ack_ready = (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 100 : 1);
|
||||
if(top->dBus_sync_ready) top->dBus_sync_valid = 0;
|
||||
if(top->dBus_sync_valid == 0 && pendingSync != 0 && (ws->dStall ? VL_RANDOM_I(7) < 80 : 1) ){
|
||||
if(top->dBus_sync_valid == 0 && pendingSync != 0 && (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 80 : 1) ){
|
||||
top->dBus_sync_valid = 1;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2766,7 +2771,7 @@ public:
|
|||
}
|
||||
|
||||
virtual void postCycle(){
|
||||
if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I(7) < 100)){
|
||||
if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I_WIDTH(7) < 100)){
|
||||
DBusCachedAvalonTask rsp = rsps.front();
|
||||
rsps.pop();
|
||||
top->dBusAvalon_response = rsp.error ? 3 : 0;
|
||||
|
|
@ -2774,11 +2779,11 @@ public:
|
|||
top->dBusAvalon_readDataValid = 1;
|
||||
} else{
|
||||
top->dBusAvalon_readDataValid = 0;
|
||||
top->dBusAvalon_readData = VL_RANDOM_I(32);
|
||||
top->dBusAvalon_response = VL_RANDOM_I(2); //TODO
|
||||
top->dBusAvalon_readData = VL_RANDOM_I_WIDTH(32);
|
||||
top->dBusAvalon_response = VL_RANDOM_I_WIDTH(2); //TODO
|
||||
}
|
||||
|
||||
top->dBusAvalon_waitRequestn = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1);
|
||||
top->dBusAvalon_waitRequestn = (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 100 : 1);
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -3007,9 +3012,9 @@ public:
|
|||
top->debug_bus_cmd_payload_data = task.data;
|
||||
}else {
|
||||
top->debug_bus_cmd_valid = 0;
|
||||
top->debug_bus_cmd_payload_wr = VL_RANDOM_I(1);
|
||||
top->debug_bus_cmd_payload_address = VL_RANDOM_I(8);
|
||||
top->debug_bus_cmd_payload_data = VL_RANDOM_I(32);
|
||||
top->debug_bus_cmd_payload_wr = VL_RANDOM_I_WIDTH(1);
|
||||
top->debug_bus_cmd_payload_address = VL_RANDOM_I_WIDTH(8);
|
||||
top->debug_bus_cmd_payload_data = VL_RANDOM_I_WIDTH(32);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
@ -3058,8 +3063,8 @@ public:
|
|||
}else {
|
||||
top->debugBusAvalon_write = 0;
|
||||
top->debugBusAvalon_read = 0;
|
||||
top->debugBusAvalon_address = VL_RANDOM_I(8);
|
||||
top->debugBusAvalon_writeData = VL_RANDOM_I(32);
|
||||
top->debugBusAvalon_address = VL_RANDOM_I_WIDTH(8);
|
||||
top->debugBusAvalon_writeData = VL_RANDOM_I_WIDTH(32);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
@ -3372,7 +3377,7 @@ public:
|
|||
|
||||
|
||||
uint32_t readCmd(uint32_t size, uint32_t address){
|
||||
accessCmd(false, 2, address, VL_RANDOM_I(32));
|
||||
accessCmd(false, 2, address, VL_RANDOM_I_WIDTH(32));
|
||||
int error;
|
||||
if((error = recv(clientSocket, buffer, 4, 0)) != 4){
|
||||
printf("Should read 4 bytes, had %d", error);
|
||||
|
|
@ -4433,7 +4438,7 @@ int main(int argc, char **argv, char **env) {
|
|||
}
|
||||
|
||||
while(tasks.size() > FREERTOS_COUNT){
|
||||
tasks.erase(tasks.begin() + (VL_RANDOM_I(32)%tasks.size()));
|
||||
tasks.erase(tasks.begin() + (VL_RANDOM_I_WIDTH(32)%tasks.size()));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -4464,7 +4469,7 @@ int main(int argc, char **argv, char **env) {
|
|||
}
|
||||
|
||||
while(tasks.size() > ZEPHYR_COUNT){
|
||||
tasks.erase(tasks.begin() + (VL_RANDOM_I(32)%tasks.size()));
|
||||
tasks.erase(tasks.begin() + (VL_RANDOM_I_WIDTH(32)%tasks.size()));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
2
tools.sh
2
tools.sh
|
|
@ -6,7 +6,7 @@ install_verilator(){
|
|||
unset VERILATOR_ROOT # For bash
|
||||
cd verilator
|
||||
git pull # Make sure we're up-to-date
|
||||
git checkout v4.040
|
||||
git checkout v4.216
|
||||
autoconf # Create ./configure script
|
||||
./configure --prefix ~/tools
|
||||
make -j$(nproc)
|
||||
|
|
|
|||
Loading…
Reference in a new issue