Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value
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@ -25,7 +25,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
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val debugClockDomain = Handle[ClockDomain]
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val debugReset = Handle[Bool]
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val debugAskReset = Handle[() => Unit]
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val hardwareBreakpointCount = Handle(0)
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val hardwareBreakpointCount = Handle.sync(0)
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val iBus, dBus = Handle[Bmb]
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