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VexRiscv
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Merge branch 'dev' (fix FPU dirty flag on csr write)

This commit is contained in:
Dolu1990 2022-10-13 09:35:55 +02:00
parent 7b9891829a 959e48a353
commit 87c8822f55
2 changed files with 6 additions and 3 deletions
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3
src/main/scala/vexriscv/plugin/FpuPlugin.scala
View File

@ -219,6 +219,9 @@ class FpuPlugin(externalFpu : Boolean = false,
when(stages.last.arbitration.isFiring && stages.last.input(FPU_ENABLE) && stages.last.input(FPU_OPCODE) =/= FpuOpcode.STORE){
fs := 3 //DIRTY
}
when(List(CSR.FRM, CSR.FCSR, CSR.FFLAGS).map(id => service.isWriting(id)).orR){
fs := 3
}
service.rw(CSR.SSTATUS, 13, fs)
service.rw(CSR.MSTATUS, 13, fs)

6
src/test/cpp/regression/main.cpp
View File

@ -668,9 +668,9 @@ public:
case SATP: satp.raw = value; break;
#ifdef RVF
case FCSR: fcsr.raw = value & 0x7F; break;
case FRM: fcsr.frm = value; break;
case FFLAGS: fcsr.flags = value; break;
case FCSR: fcsr.raw = value & 0x7F; status.fs = 3; break;
case FRM: fcsr.frm = value; status.fs = 3; break;
case FFLAGS: fcsr.flags = value; status.fs = 3; break;
#endif
default: ilegalInstruction(); return true; break;