Cleaning/Add documentation
This commit is contained in:
Charles Papon
parent
835dd4ad50
commit
88a2c4a603
89
README.md
89
README.md
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@ -20,76 +20,47 @@ The hardware description of this CPU is done by using an very software oriented
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- There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline.
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## CPU instantiation
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There is an example of instantiation of the CPU
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## CPU generation
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You can find two example of CPU instantiation in :
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- src/main/scala/VexRiscv/GenFull.scala
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- src/main/scala/VexRiscv/GenSmallest.scala
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```scala
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//Define the cpu configuraiton
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val config = VexRiscvConfig(
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pcWidth = 32
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)
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To generate the corresponding RTL as a VexRiscv.v file, run :
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//Define the CSR configuration (riscv-privileged-v1.9.1)
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val csrConfig = MachineCsrConfig(
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mvendorid = 11,
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marchid = 22,
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mimpid = 33,
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mhartid = 0,
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.READ_WRITE,
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mtvecAccess = CsrAccess.READ_WRITE,
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mtvecInit = 0x00000020l,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = true,
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mcauseAccess = CsrAccess.READ_WRITE,
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mbadaddrAccess = CsrAccess.READ_WRITE,
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mcycleAccess = CsrAccess.READ_WRITE,
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minstretAccess = CsrAccess.READ_WRITE,
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ecallGen = true,
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wfiGen = true
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)
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```sh
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sbt run-main VexRiscv.GenFull
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//Add plugins into the cpu configuration
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config.plugins ++= List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(
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interfaceKeepData = true
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin,
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new FullBarrielShifterPlugin,
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new DBusSimplePlugin(
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catchUnalignedException = true
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),
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new HazardSimplePlugin(true, true, true, true),
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new MulPlugin,
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new DivPlugin,
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new MachineCsr(csrConfig),
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new BranchPlugin(
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earlyBranch = false,
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catchUnalignedException = true,
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prediction = DYNAMIC
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)
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)
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# or
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sbt run-main VexRiscv.GenSmallest
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```
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//Instanciate the CPU
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val toplevel = new VexRiscv(config)
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## Tests
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To run tests (need the verilator simulator), go in the src/test/cpp/regression folder and run :
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```sh
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# To test the GenFull CPU
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make clean run
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# To test the GenSmallest CPU
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make clean run IBUS=IBUS_SIMPLE DBUS=DBUS_SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no
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```
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## Interactive debug of the simulated CPU via GDB/OpenOCD in Verilator
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It's as described to run tests, but you just have to add DEBUG_PLUGIN_EXTERNAL=yes in the make arguments.
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Work for the GenFull, but not for the GenSmallest as this configuration has no debug module.
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Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a GDB server connected to the target (the simulated CPU)
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```sh
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src/openocd -c "set VEXRISCV_YAML PATH_TO_THE_GENERATED_CPU0_YAML_FILE" -f tcl/target/vexriscv_sim.cfg
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```
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## Plugin structure
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## Cpu plugin structure
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There is an example of an pseudo ALU plugin :
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```scala
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//Define an signal name/type which could be used in the pipeline
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object ALU_ENABLE extends Stageable(Bool)
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object ALU_OP extends Stageable(Bits(2 bits)) // ADD, SUB, AND, OR
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40
cpu0.yaml
40
cpu0.yaml
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@ -1,40 +0,0 @@
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dBus: !!SpinalRiscv.BusReport
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flushInstructions: [147, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455,
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33587347, 1879101455]
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info: !!SpinalRiscv.CacheReport {bytePerLine: 32, size: 4096}
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kind: cached
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iBus: !!SpinalRiscv.BusReport
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flushInstructions: [16399]
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info: !!SpinalRiscv.CacheReport {bytePerLine: 32, size: 4096}
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kind: cached
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@ -0,0 +1,93 @@
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package VexRiscv
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import VexRiscv.Plugin._
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import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import spinal.core._
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/**
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* Created by spinalvm on 15.06.17.
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*/
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object GenFull extends App{
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SpinalVerilog(
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gen = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoStageLogic = true
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),
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askMemoryTranslation = true,
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 4
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)
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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),
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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virtualRange = _(31 downto 28) === 0xC,
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new FullBarrielShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new MulPlugin,
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new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = DYNAMIC
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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)
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}
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@ -0,0 +1,56 @@
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package VexRiscv
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import VexRiscv.Plugin._
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import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import spinal.core._
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/**
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* Created by spinalvm on 15.06.17.
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*/
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object GenSmallest extends App{
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SpinalVerilog(
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gen = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, true),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new CsrPlugin(CsrPluginConfig.smallest),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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)
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}
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@ -1,6 +1,6 @@
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package SpinalRiscv
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package VexRiscv
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import SpinalRiscv.Plugin._
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import VexRiscv.Plugin._
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import spinal.core._
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import spinal.lib._
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@ -1,7 +1,7 @@
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package SpinalRiscv.Plugin
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package VexRiscv.Plugin
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import SpinalRiscv.Riscv._
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import SpinalRiscv._
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import VexRiscv.Riscv._
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import VexRiscv._
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import spinal.core._
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import spinal.lib._
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@ -1,9 +1,9 @@
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package SpinalRiscv.Plugin
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package VexRiscv.Plugin
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import spinal.core._
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import spinal.lib._
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import SpinalRiscv._
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import SpinalRiscv.Riscv._
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import VexRiscv._
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import VexRiscv.Riscv._
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.mutable
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@ -31,7 +31,7 @@ object CsrAccess {
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}
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case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int)
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case class MachineCsrConfig(
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case class csrPluginConfig(
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catchIllegalAccess : Boolean,
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mvendorid : BigInt,
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marchid : BigInt,
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@ -54,7 +54,71 @@ case class MachineCsrConfig(
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assert(!ucycleAccess.canWrite)
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}
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object CsrPluginConfig{
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val all = csrPluginConfig(
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catchIllegalAccess = true,
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mvendorid = 11,
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marchid = 22,
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mimpid = 33,
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mhartid = 0,
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.READ_WRITE,
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mtvecAccess = CsrAccess.READ_WRITE,
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mtvecInit = 0x00000020l,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = true,
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mcauseAccess = CsrAccess.READ_WRITE,
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mbadaddrAccess = CsrAccess.READ_WRITE,
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mcycleAccess = CsrAccess.READ_WRITE,
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minstretAccess = CsrAccess.READ_WRITE,
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ecallGen = true,
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wfiGen = true,
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ucycleAccess = CsrAccess.READ_ONLY
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)
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val small = csrPluginConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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mimpid = null,
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mhartid = null,
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.NONE,
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mtvecInit = 0x00000020l,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = false,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ecallGen = false,
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wfiGen = false,
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ucycleAccess = CsrAccess.NONE
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)
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val smallest = csrPluginConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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mimpid = null,
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mhartid = null,
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.NONE,
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mtvecInit = 0x00000020l,
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mepcAccess = CsrAccess.READ_ONLY,
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mscratchGen = false,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.NONE,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ecallGen = false,
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wfiGen = false,
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ucycleAccess = CsrAccess.NONE
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)
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}
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case class CsrWrite(that : Data, bitOffset : Int)
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case class CsrRead(that : Data , bitOffset : Int)
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case class CsrMapping(){
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@ -76,7 +140,7 @@ case class CsrMapping(){
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class CsrPlugin(config : MachineCsrConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor{
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class CsrPlugin(config : csrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor{
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import config._
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import CsrAccess._
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@ -1,7 +1,7 @@
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package SpinalRiscv.Plugin
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package VexRiscv.Plugin
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import SpinalRiscv.ip._
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import SpinalRiscv._
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import VexRiscv.ip._
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import VexRiscv._
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import spinal.core._
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import spinal.lib._
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@ -1,6 +1,6 @@
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package SpinalRiscv.Plugin
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package VexRiscv.Plugin
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import SpinalRiscv._
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import VexRiscv._
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi._
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@ -1,8 +1,8 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv.Plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL}
|
||||
import SpinalRiscv._
|
||||
import SpinalRiscv.ip._
|
||||
import VexRiscv.Plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL}
|
||||
import VexRiscv._
|
||||
import VexRiscv.ip._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
import spinal.lib.bus.amba3.apb.{Apb3Config, Apb3}
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv.{VexRiscv, _}
|
||||
import VexRiscv.{VexRiscv, _}
|
||||
import spinal.core._
|
||||
import spinal.lib.math.MixedDivider
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import SpinalRiscv.ip._
|
||||
import VexRiscv._
|
||||
import VexRiscv.ip._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv}
|
||||
import VexRiscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv}
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
import spinal.lib.bus.amba4.axi._
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
object IntAluPlugin{
|
||||
object AluBitwiseCtrlEnum extends SpinalEnum(binarySequential){
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv.{VexRiscv, _}
|
||||
import VexRiscv.{VexRiscv, _}
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
import SpinalRiscv._
|
||||
import SpinalRiscv.VexRiscv
|
||||
package VexRiscv.Plugin
|
||||
import VexRiscv._
|
||||
import VexRiscv.VexRiscv
|
||||
import spinal.core._
|
||||
|
||||
class MulPlugin extends Plugin[VexRiscv]{
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv.{Pipeline, Stage}
|
||||
import VexRiscv.{Pipeline, Stage}
|
||||
import spinal.core.Area
|
||||
|
||||
/**
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib.Reverse
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv.{Riscv, VexRiscv}
|
||||
import VexRiscv.{Riscv, VexRiscv}
|
||||
import spinal.core._
|
||||
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import SpinalRiscv.{VexRiscv, _}
|
||||
import VexRiscv.{VexRiscv, _}
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
package SpinalRiscv.Plugin
|
||||
package VexRiscv.Plugin
|
||||
|
||||
import java.util
|
||||
|
||||
import SpinalRiscv.{ReportService, VexRiscv}
|
||||
import VexRiscv.{ReportService, VexRiscv}
|
||||
import org.yaml.snakeyaml.{DumperOptions, Yaml}
|
||||
|
||||
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
package SpinalRiscv
|
||||
package VexRiscv
|
||||
|
||||
import spinal.core._
|
||||
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
package SpinalRiscv
|
||||
package VexRiscv
|
||||
|
||||
import java.util
|
||||
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
package SpinalRiscv
|
||||
package VexRiscv
|
||||
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
|
|
@ -16,92 +16,16 @@
|
|||
* License along with this library.
|
||||
*/
|
||||
|
||||
package SpinalRiscv
|
||||
package VexRiscv
|
||||
|
||||
import SpinalRiscv.Plugin._
|
||||
import VexRiscv.Plugin._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
import SpinalRiscv.ip._
|
||||
import VexRiscv.ip._
|
||||
|
||||
object TopLevel {
|
||||
object TestsWorkspace {
|
||||
def main(args: Array[String]) {
|
||||
SpinalVerilog {
|
||||
|
||||
|
||||
// val iCacheConfig = InstructionCacheConfig(
|
||||
// cacheSize =4096,
|
||||
// bytePerLine =32,
|
||||
// wayCount = 1,
|
||||
// wrappedMemAccess = true,
|
||||
// addressWidth = 32,
|
||||
// cpuDataWidth = 32,
|
||||
// memDataWidth = 32
|
||||
// )
|
||||
|
||||
|
||||
val csrConfigAll = MachineCsrConfig(
|
||||
catchIllegalAccess = true,
|
||||
mvendorid = 11,
|
||||
marchid = 22,
|
||||
mimpid = 33,
|
||||
mhartid = 0,
|
||||
misaExtensionsInit = 66,
|
||||
misaAccess = CsrAccess.READ_WRITE,
|
||||
mtvecAccess = CsrAccess.READ_WRITE,
|
||||
mtvecInit = 0x00000020l,
|
||||
mepcAccess = CsrAccess.READ_WRITE,
|
||||
mscratchGen = true,
|
||||
mcauseAccess = CsrAccess.READ_WRITE,
|
||||
mbadaddrAccess = CsrAccess.READ_WRITE,
|
||||
mcycleAccess = CsrAccess.READ_WRITE,
|
||||
minstretAccess = CsrAccess.READ_WRITE,
|
||||
ecallGen = true,
|
||||
wfiGen = true,
|
||||
ucycleAccess = CsrAccess.READ_ONLY
|
||||
)
|
||||
|
||||
val csrConfigSmall = MachineCsrConfig(
|
||||
catchIllegalAccess = false,
|
||||
mvendorid = null,
|
||||
marchid = null,
|
||||
mimpid = null,
|
||||
mhartid = null,
|
||||
misaExtensionsInit = 66,
|
||||
misaAccess = CsrAccess.NONE,
|
||||
mtvecAccess = CsrAccess.NONE,
|
||||
mtvecInit = 0x00000020l,
|
||||
mepcAccess = CsrAccess.READ_WRITE,
|
||||
mscratchGen = false,
|
||||
mcauseAccess = CsrAccess.READ_ONLY,
|
||||
mbadaddrAccess = CsrAccess.READ_ONLY,
|
||||
mcycleAccess = CsrAccess.NONE,
|
||||
minstretAccess = CsrAccess.NONE,
|
||||
ecallGen = false,
|
||||
wfiGen = false,
|
||||
ucycleAccess = CsrAccess.NONE
|
||||
)
|
||||
|
||||
val csrConfigSmallest = MachineCsrConfig(
|
||||
catchIllegalAccess = false,
|
||||
mvendorid = null,
|
||||
marchid = null,
|
||||
mimpid = null,
|
||||
mhartid = null,
|
||||
misaExtensionsInit = 66,
|
||||
misaAccess = CsrAccess.NONE,
|
||||
mtvecAccess = CsrAccess.NONE,
|
||||
mtvecInit = 0x00000020l,
|
||||
mepcAccess = CsrAccess.READ_ONLY,
|
||||
mscratchGen = false,
|
||||
mcauseAccess = CsrAccess.READ_ONLY,
|
||||
mbadaddrAccess = CsrAccess.NONE,
|
||||
mcycleAccess = CsrAccess.NONE,
|
||||
minstretAccess = CsrAccess.NONE,
|
||||
ecallGen = false,
|
||||
wfiGen = false,
|
||||
ucycleAccess = CsrAccess.NONE
|
||||
)
|
||||
|
||||
val configFull = VexRiscvConfig(
|
||||
plugins = List(
|
||||
new PcManagerSimplePlugin(0x00000000l, false),
|
||||
|
|
@ -185,7 +109,7 @@ object TopLevel {
|
|||
// new HazardSimplePlugin(false, false, false, false),
|
||||
new MulPlugin,
|
||||
new DivPlugin,
|
||||
new CsrPlugin(csrConfigAll),
|
||||
new CsrPlugin(CsrPluginConfig.all),
|
||||
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
|
||||
new BranchPlugin(
|
||||
earlyBranch = false,
|
||||
|
|
@ -259,7 +183,7 @@ object TopLevel {
|
|||
catchAddressMisaligned = true,
|
||||
catchAccessFault = true
|
||||
),
|
||||
new CsrPlugin(csrConfigSmall),
|
||||
new CsrPlugin(CsrPluginConfig.small),
|
||||
new DecoderSimplePlugin(
|
||||
catchIllegalInstruction = true
|
||||
),
|
||||
|
|
@ -298,10 +222,6 @@ object TopLevel {
|
|||
val toplevel = new VexRiscv(configFull)
|
||||
// val toplevel = new VexRiscv(configLight)
|
||||
// val toplevel = new VexRiscv(configTest)
|
||||
toplevel.decode.input(toplevel.config.INSTRUCTION).addAttribute(Verilator.public)
|
||||
toplevel.decode.input(toplevel.config.PC).addAttribute(Verilator.public)
|
||||
toplevel.decode.arbitration.isValid.addAttribute(Verilator.public)
|
||||
toplevel.decode.arbitration.haltIt.addAttribute(Verilator.public)
|
||||
// toplevel.writeBack.input(config.PC).addAttribute(Verilator.public)
|
||||
// toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv
|
||||
package VexRiscv
|
||||
|
||||
import SpinalRiscv.Plugin.Plugin
|
||||
import VexRiscv.Plugin.Plugin
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
import scala.collection.mutable.ArrayBuffer
|
||||
|
|
@ -56,6 +56,10 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
|
|||
plugins ++= config.plugins
|
||||
|
||||
//regression usage
|
||||
decode.input(config.INSTRUCTION).addAttribute(Verilator.public)
|
||||
decode.input(config.PC).addAttribute(Verilator.public)
|
||||
decode.arbitration.isValid.addAttribute(Verilator.public)
|
||||
decode.arbitration.haltIt.addAttribute(Verilator.public)
|
||||
writeBack.input(config.INSTRUCTION) keep() addAttribute(Verilator.public)
|
||||
writeBack.input(config.PC) keep() addAttribute(Verilator.public)
|
||||
writeBack.arbitration.isValid keep() addAttribute(Verilator.public)
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
package SpinalRiscv.demo
|
||||
package VexRiscv.demo
|
||||
|
||||
|
||||
import SpinalRiscv.Plugin._
|
||||
import SpinalRiscv._
|
||||
import SpinalRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
|
||||
import VexRiscv.Plugin._
|
||||
import VexRiscv._
|
||||
import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
import spinal.lib.bus.amba3.apb._
|
||||
|
|
@ -265,7 +265,7 @@ class Briey(config: BrieyConfig) extends Component{
|
|||
prediction = STATIC
|
||||
),
|
||||
new CsrPlugin(
|
||||
config = MachineCsrConfig(
|
||||
config = csrPluginConfig(
|
||||
catchIllegalAccess = false,
|
||||
mvendorid = null,
|
||||
marchid = null,
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.ip
|
||||
package VexRiscv.ip
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
import spinal.lib.bus.amba4.axi.{Axi4Shared, Axi4Config}
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
package SpinalRiscv.ip
|
||||
package VexRiscv.ip
|
||||
|
||||
import SpinalRiscv._
|
||||
import VexRiscv._
|
||||
import spinal.core._
|
||||
import spinal.lib._
|
||||
import spinal.lib.bus.amba4.axi.{Axi4ReadOnly, Axi4Config}
|
||||
|
|
@ -39,7 +39,12 @@ public:
|
|||
uint8_t* get(uint32_t address){
|
||||
if(mem[address >> 20] == NULL) {
|
||||
uint8_t* ptr = new uint8_t[1024*1024];
|
||||
for(uint32_t i = 0;i < 1024*1024;i++) ptr[i] = 0xFF;
|
||||
for(uint32_t i = 0;i < 1024*1024;i+=4) {
|
||||
ptr[i + 0] = 0xFF;
|
||||
ptr[i + 1] = 0xFF;
|
||||
ptr[i + 2] = 0xFF;
|
||||
ptr[i + 3] = 0xFF;
|
||||
}
|
||||
mem[address >> 20] = ptr;
|
||||
}
|
||||
return &mem[address >> 20][address & 0xFFFFF];
|
||||
|
|
@ -223,7 +228,7 @@ public:
|
|||
virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error) {
|
||||
if(addr % 4 != 0) {
|
||||
cout << "Warning, unaligned IBusAccess : " << addr << endl;
|
||||
fail();
|
||||
// fail();
|
||||
}
|
||||
*data = ( (mem[addr + 0] << 0)
|
||||
| (mem[addr + 1] << 8)
|
||||
|
|
@ -461,7 +466,7 @@ public:
|
|||
|
||||
virtual void preCycle(){
|
||||
if (top->iBus_cmd_valid && top->iBus_cmd_ready && !pending) {
|
||||
assertEq(top->iBus_cmd_payload_pc & 3,0);
|
||||
//assertEq(top->iBus_cmd_payload_pc & 3,0);
|
||||
pending = true;
|
||||
ws->iBusAccess(top->iBus_cmd_payload_pc,&inst_next,&error_next);
|
||||
}
|
||||
|
|
@ -966,7 +971,7 @@ public:
|
|||
}
|
||||
};
|
||||
|
||||
|
||||
#ifdef DEBUG_PLUGIN
|
||||
|
||||
#include<pthread.h>
|
||||
#include<stdlib.h>
|
||||
|
|
@ -1137,6 +1142,7 @@ public:
|
|||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
string riscvTestMain[] = {
|
||||
"rv32ui-p-simple",
|
||||
|
|
@ -1223,67 +1229,75 @@ int main(int argc, char **argv, char **env) {
|
|||
for(int idx = 0;idx < 1;idx++){
|
||||
#ifndef REF
|
||||
|
||||
#ifdef DEBUG_PLUGIN_EXTERNAL
|
||||
{
|
||||
Workspace w("debugPluginExternal");
|
||||
w.loadHex("../../resources/hex/debugPluginExternal.hex");
|
||||
w.noInstructionReadCheck();
|
||||
#if defined(TRACE) || defined(TRACE_ACCESS)
|
||||
w.setCyclesPerSecond(5e3);
|
||||
printf("Speed reduced 5Khz\n");
|
||||
#ifdef DEBUG_PLUGIN_EXTERNAL
|
||||
{
|
||||
Workspace w("debugPluginExternal");
|
||||
w.loadHex("../../resources/hex/debugPluginExternal.hex");
|
||||
w.noInstructionReadCheck();
|
||||
#if defined(TRACE) || defined(TRACE_ACCESS)
|
||||
w.setCyclesPerSecond(5e3);
|
||||
printf("Speed reduced 5Khz\n");
|
||||
#endif
|
||||
w.run(1e9);
|
||||
}
|
||||
#endif
|
||||
w.run(1e9);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
TestA().run();
|
||||
TestA().run();
|
||||
|
||||
|
||||
|
||||
|
||||
for(const string &name : riscvTestMain){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
for(const string &name : riscvTestMemory){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
for(const string &name : riscvTestMul){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
for(const string &name : riscvTestDiv){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
for(const string &name : riscvTestMain){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
for(const string &name : riscvTestMemory){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
#ifdef MUL
|
||||
for(const string &name : riscvTestMul){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
#endif
|
||||
#ifdef DIV
|
||||
for(const string &name : riscvTestDiv){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CSR
|
||||
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
|
||||
8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 };
|
||||
redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).noInstructionReadCheck()->run(4e3);)
|
||||
#endif
|
||||
#ifdef MMU
|
||||
uint32_t mmuRef[] = {1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5,
|
||||
13, 0xC4000000,0x33333333, 6,7,
|
||||
1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5,
|
||||
13, 0xC4000000,0x33333333, 6,7};
|
||||
redo(REDO,TestX28("mmu",mmuRef, sizeof(mmuRef)/4).noInstructionReadCheck()->run(4e3);)
|
||||
#endif
|
||||
#ifdef CSR
|
||||
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
|
||||
8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 };
|
||||
redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).noInstructionReadCheck()->run(4e3);)
|
||||
#endif
|
||||
#ifdef MMU
|
||||
uint32_t mmuRef[] = {1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5,
|
||||
13, 0xC4000000,0x33333333, 6,7,
|
||||
1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5,
|
||||
13, 0xC4000000,0x33333333, 6,7};
|
||||
redo(REDO,TestX28("mmu",mmuRef, sizeof(mmuRef)/4).noInstructionReadCheck()->run(4e3);)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_PLUGIN
|
||||
redo(REDO,DebugPluginTest().run(1e6););
|
||||
redo(REDO,DebugPluginTest().run(1e6););
|
||||
#endif
|
||||
|
||||
#ifdef DHRYSTONE
|
||||
Dhrystone("dhrystoneO3_Stall","dhrystoneO3",true,true).run(1.1e6);
|
||||
Dhrystone("dhrystoneO3M_Stall","dhrystoneO3M",true,true).run(1.5e6);
|
||||
Dhrystone("dhrystoneO3","dhrystoneO3",false,false).run(1.5e6);
|
||||
Dhrystone("dhrystoneO3M","dhrystoneO3M",false,false).run(1.2e6);
|
||||
Dhrystone("dhrystoneO3_Stall","dhrystoneO3",true,true).run(1.1e6);
|
||||
#if defined(MUL) || defined(DIV)
|
||||
Dhrystone("dhrystoneO3M_Stall","dhrystoneO3M",true,true).run(1.5e6);
|
||||
#endif
|
||||
Dhrystone("dhrystoneO3","dhrystoneO3",false,false).run(1.5e6);
|
||||
#if defined(MUL) || defined(DIV)
|
||||
Dhrystone("dhrystoneO3M","dhrystoneO3M",false,false).run(1.2e6);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef FREE_RTOS
|
||||
redo(1,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);)
|
||||
redo(1,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);)
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
IBUS=IBUS_CACHED
|
||||
DBUS=DBUS_CACHED
|
||||
IBUS?=IBUS_CACHED
|
||||
DBUS?=DBUS_CACHED
|
||||
TRACE?=no
|
||||
TRACE_ACCESS?=no
|
||||
TRACE_START=0
|
||||
CSR=yes
|
||||
MMU=yes
|
||||
DEBUG_PLUGIN=yes
|
||||
MUL?=yes
|
||||
DIV?=yes
|
||||
CSR?=yes
|
||||
MMU?=yes
|
||||
DEBUG_PLUGIN?=yes
|
||||
DEBUG_PLUGIN_EXTERNAL?=no
|
||||
DHRYSTONE=yes
|
||||
FREE_RTOS=no
|
||||
REDO=10
|
||||
REDO?=10
|
||||
REF=no
|
||||
TRACE_WITH_TIME=no
|
||||
REF_TIME=no
|
||||
|
|
@ -45,6 +47,14 @@ ifeq ($(MMU),yes)
|
|||
ADDCFLAGS += -CFLAGS -DMMU
|
||||
endif
|
||||
|
||||
ifeq ($(MUL),yes)
|
||||
ADDCFLAGS += -CFLAGS -DMUL
|
||||
endif
|
||||
|
||||
ifeq ($(DIV),yes)
|
||||
ADDCFLAGS += -CFLAGS -DDIV
|
||||
endif
|
||||
|
||||
ifeq ($(TRACE_ACCESS),yes)
|
||||
ADDCFLAGS += -CFLAGS -DTRACE_ACCESS
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue