Add rvc support and fix rvc with FPU
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@ -115,6 +115,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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var aesInstruction = false
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var fpu = false
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var cpuPerFpu = 4
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var rvc = false
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var netlistDirectory = "."
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var netlistName = "VexRiscvLitexSmpCluster"
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assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
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@ -135,6 +136,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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opt[String]("wishbone-memory" ) action { (v, c) => wishboneMemory = v.toBoolean }
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opt[String]("fpu" ) action { (v, c) => fpu = v.toBoolean }
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opt[String]("cpu-per-fpu") action { (v, c) => cpuPerFpu = v.toInt }
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opt[String]("rvc") action { (v, c) => rvc = v.toBoolean }
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}.parse(args))
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val coherency = coherentDma || cpuCount > 1
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@ -157,7 +159,9 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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withFloat = fpu,
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withDouble = fpu,
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externalFpu = fpu,
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loadStoreWidth = if(fpu) 64 else 32
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loadStoreWidth = if(fpu) 64 else 32,
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rvc = rvc,
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injectorStage = rvc
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)
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if(aesInstruction) c.add(new AesPlugin)
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c
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