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Add rvc support and fix rvc with FPU

This commit is contained in:
Dolu1990 2021-03-25 14:14:19 +01:00
parent 6f481f51ef
commit 9462496386
1 changed files with 5 additions and 1 deletions
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6
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -115,6 +115,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
var aesInstruction = false var aesInstruction = false
var fpu = false var fpu = false
var cpuPerFpu = 4 var cpuPerFpu = 4
var rvc = false
var netlistDirectory = "." var netlistDirectory = "."
var netlistName = "VexRiscvLitexSmpCluster" var netlistName = "VexRiscvLitexSmpCluster"
assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") { assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
@ -135,6 +136,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
opt[String]("wishbone-memory" ) action { (v, c) => wishboneMemory = v.toBoolean } opt[String]("wishbone-memory" ) action { (v, c) => wishboneMemory = v.toBoolean }
opt[String]("fpu" ) action { (v, c) => fpu = v.toBoolean } opt[String]("fpu" ) action { (v, c) => fpu = v.toBoolean }
opt[String]("cpu-per-fpu") action { (v, c) => cpuPerFpu = v.toInt } opt[String]("cpu-per-fpu") action { (v, c) => cpuPerFpu = v.toInt }
opt[String]("rvc") action { (v, c) => rvc = v.toBoolean }
}.parse(args)) }.parse(args))
val coherency = coherentDma || cpuCount > 1 val coherency = coherentDma || cpuCount > 1
@ -157,7 +159,9 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
withFloat = fpu, withFloat = fpu,
withDouble = fpu, withDouble = fpu,
externalFpu = fpu, externalFpu = fpu,
loadStoreWidth = if(fpu) 64 else 32 loadStoreWidth = if(fpu) 64 else 32,
rvc = rvc,
injectorStage = rvc
) )
if(aesInstruction) c.add(new AesPlugin) if(aesInstruction) c.add(new AesPlugin)
c c