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Avalon: Debug Clock Domain for JTAG

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This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
This commit is contained in:
Brett Foster 2018-12-22 07:58:59 -08:00
parent 6334f430fe
commit 961abb3cf1
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
View file

@ -162,7 +162,7 @@ object VexRiscvAvalonWithIntegratedJtag{
.setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DebugPlugin => {
case plugin: DebugPlugin => plugin.debugClockDomain {
plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag())
.setName("jtag")

2
src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
View file

@ -163,7 +163,7 @@ object VexRiscvAxi4WithIntegratedJtag{
.setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DebugPlugin => {
case plugin: DebugPlugin => plugin.debugClockDomain {
plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag())
.setName("jtag")