Add Uart monitor in the briey testbench
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@ -30,12 +30,12 @@ public:
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};
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//#include <functional>
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class Process{
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class TimeProcess{
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public:
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uint64_t wakeDelay = 0;
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bool wakeEnable = false;
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// std::function<int(double)> lambda;
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virtual ~Process(){}
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virtual ~TimeProcess(){}
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virtual void schedule(uint64_t delay){
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wakeDelay = delay;
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wakeEnable = true;
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@ -47,7 +47,16 @@ public:
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};
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class ClockDomain : public Process{
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class SensitiveProcess{
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public:
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virtual ~SensitiveProcess(){}
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virtual void tick(uint64_t time){
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}
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};
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class ClockDomain : public TimeProcess{
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public:
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CData* clk;
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CData* reset;
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@ -91,7 +100,7 @@ public:
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};
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class AsyncReset : public Process{
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class AsyncReset : public TimeProcess{
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public:
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CData* reset;
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uint32_t state;
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@ -144,7 +153,7 @@ bool SetSocketBlockingEnabled(int fd, bool blocking)
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#endif
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}
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class Jtag : public Process{
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class Jtag : public TimeProcess{
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public:
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CData *tms, *tdi, *tdo, *tck;
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enum State {reset};
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@ -268,7 +277,8 @@ class success : public std::exception { };
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class Workspace{
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public:
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static uint32_t cycles;
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vector<Process*> processes;
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vector<TimeProcess*> timeProcesses;
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vector<SensitiveProcess*> checkProcesses;
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VBriey* top;
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bool resetDone = false;
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double timeToSec = 1e-12;
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@ -294,7 +304,8 @@ public:
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delete tfp;
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#endif
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for(Process* p : processes) delete p;
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for(auto* p : timeProcesses) delete p;
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for(auto* p : checkProcesses) delete p;
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}
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@ -338,7 +349,7 @@ public:
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try {
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while(1){
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uint64_t delay = ~0l;
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for(Process* p : processes)
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for(TimeProcess* p : timeProcesses)
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if(p->wakeEnable && p->wakeDelay < delay)
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delay = p->wakeDelay;
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@ -348,7 +359,7 @@ public:
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if(delay != 0){
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dump(time);
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}
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for(Process* p : processes) {
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for(TimeProcess* p : timeProcesses) {
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p->wakeDelay -= delay;
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if(p->wakeDelay == 0){
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p->wakeEnable = false;
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@ -357,7 +368,7 @@ public:
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}
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top->eval();
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for(auto* p : checkProcesses) p->tick(time);
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if(delay != 0){
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if(time - tickLastSimTime > 1000*400000 || time - tickLastSimTime > 1.0*speedFactor/timeToSec){
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@ -366,7 +377,9 @@ public:
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uint64_t diffInNanos = end_time.tv_sec*1e9 + end_time.tv_nsec - tick_time.tv_sec*1e9 - tick_time.tv_nsec;
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tick_time = end_time;
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double dt = diffInNanos*1e-9;
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printf("Simulation speed : %f ms/realTime\n",(time - tickLastSimTime)/dt*timeToSec*1e3);
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#ifdef PRINT_PERF
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printf("Simulation speed : %f ms/realTime\n",(time - tickLastSimTime)/dt*timeToSec*1e3);
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#endif
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tickLastSimTime = time;
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}
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time += delay;
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@ -387,7 +400,7 @@ public:
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if(flushCounter > 100000){
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#ifdef TRACE
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tfp->flush();
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printf("flush\n");
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//printf("flush\n");
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#endif
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flushCounter = 0;
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}
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@ -620,6 +633,62 @@ public:
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}
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};
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class UartRx : public SensitiveProcess{
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public:
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CData *rx;
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uint32_t uartTimeRate;
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UartRx(CData *rx, uint32_t uartTimeRate){
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this->rx = rx;
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this->uartTimeRate = uartTimeRate;
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}
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enum State {START, DATA, STOP,START_SUCCESS};
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State state = START;
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uint64_t holdTime = 0;
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CData holdValue;
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char data;
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uint32_t counter;
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virtual void tick(uint64_t time){
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if(time < holdTime){
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if(*rx != holdValue){
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cout << "UART RX FRAME ERROR" << endl;
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holdTime = time;
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state = START;
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}
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}else{
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switch(state){
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case START:
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case START_SUCCESS:
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if(state == START_SUCCESS){
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cout << data << flush;
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state = START;
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}
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if(*rx == 0 && time > uartTimeRate){
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holdTime = time + uartTimeRate;
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holdValue = *rx;
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state = DATA;
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counter = 0;
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data = 0;
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}
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break;
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case DATA:
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data |= (*rx) << counter++;
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if(counter == 8){
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state = STOP;
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}
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holdValue = *rx;
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holdTime = time + uartTimeRate;
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break;
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case STOP:
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holdTime = time + uartTimeRate;
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holdValue = 1;
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state = START_SUCCESS;
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break;
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}
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}
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}
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};
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class BrieyWorkspace : public Workspace{
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public:
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@ -628,10 +697,12 @@ public:
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ClockDomain *vgaClk = new ClockDomain(&top->io_vgaClk,NULL,40000,100000);
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AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000);
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Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,60000);
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processes.push_back(axiClk);
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processes.push_back(vgaClk);
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processes.push_back(asyncReset);
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processes.push_back(jtag);
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UartRx *uartRx = new UartRx(&top->io_uart_txd,(50000000/8/115200)*8*axiClk->tooglePeriod*2);
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timeProcesses.push_back(axiClk);
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timeProcesses.push_back(vgaClk);
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timeProcesses.push_back(asyncReset);
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timeProcesses.push_back(jtag);
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checkProcesses.push_back(uartRx);
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SdramConfig *sdramConfig = new SdramConfig(
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2, //byteCount
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@ -1,5 +1,6 @@
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DEBUG?=no
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TRACE?=no
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PRINT_PERF?=no
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TRACE_START=0
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ADDCFLAGS += -CFLAGS -pthread
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@ -13,6 +14,9 @@ endif
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ifneq ($(DEBUG),yes)
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ADDCFLAGS += -CFLAGS "-O3"
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endif
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ifeq ($(PRINT_PERF),yes)
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ADDCFLAGS += -CFLAGS -DPRINT_PERF
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endif
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ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START}
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@ -0,0 +1,60 @@
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[*]
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[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
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[*] Sat Jun 10 13:47:38 2017
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[*]
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[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd"
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[dumpfile_mtime] "Sat Jun 10 13:46:48 2017"
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[dumpfile_size] 485915260
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[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/wip.gtkw"
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[timestart] 0
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[size] 1776 953
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[pos] -775 -353
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*-18.000000 260000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TOP.
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[treeopen] TOP.Briey.
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[treeopen] TOP.Briey.axi_uartCtrl.
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[sst_width] 269
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[signals_width] 310
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[sst_expanded] 1
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[sst_vpaned_height] 503
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@28
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TOP.Briey.axi_uartCtrl.io_axiClk
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@22
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TOP.Briey.axi_uartCtrl.io_apb_PADDR[3:0]
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@28
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TOP.Briey.axi_uartCtrl.io_apb_PENABLE
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@22
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TOP.Briey.axi_uartCtrl.io_apb_PRDATA[31:0]
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@28
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TOP.Briey.axi_uartCtrl.io_apb_PREADY
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TOP.Briey.axi_uartCtrl.io_apb_PSEL[0]
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@22
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TOP.Briey.axi_uartCtrl.io_apb_PWDATA[31:0]
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@28
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TOP.Briey.axi_uartCtrl.io_apb_PWRITE
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@24
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TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_clockDivider[19:0]
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@28
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TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_dataLength[2:0]
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TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_parity[1:0]
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TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_stop[0]
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TOP.Briey.axi_uartCtrl.uartCtrl_1.io_uart_txd
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@22
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TOP.Briey.axi_core_cpu.DebugPlugin_busReadDataReg[31:0]
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@28
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TOP.Briey.axi_core_cpu.DebugPlugin_firstCycle
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TOP.Briey.axi_core_cpu.DebugPlugin_haltIt
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TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak
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TOP.Briey.axi_core_cpu.DebugPlugin_insertDecodeInstruction
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TOP.Briey.axi_core_cpu.DebugPlugin_isPipActive
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TOP.Briey.axi_core_cpu.DebugPlugin_isPipBusy
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TOP.Briey.axi_core_cpu.DebugPlugin_resetIt
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TOP.Briey.axi_core_cpu.DebugPlugin_stepIt
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TOP.Briey.axi_core_cpu.decode_IS_EBREAK
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TOP.Briey.axi_core_cpu.decode_arbitration_isValid
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@22
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TOP.Briey.axi_core_cpu.decode_PC[31:0]
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@23
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TOP.Briey.axi_core_cpu.decode_INSTRUCTION[31:0]
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[pattern_trace] 1
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[pattern_trace] 0
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