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Add Uart monitor in the briey testbench

This commit is contained in:
Charles Papon 2017-06-10 16:09:14 +02:00
parent 11a63491bd
commit 9b9d9e2582
3 changed files with 151 additions and 16 deletions
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101
src/test/cpp/briey/main.cpp
View File

@ -30,12 +30,12 @@ public:
}; };
//#include <functional> //#include <functional>
class Process{ class TimeProcess{
public: public:
uint64_t wakeDelay = 0; uint64_t wakeDelay = 0;
bool wakeEnable = false; bool wakeEnable = false;
// std::function<int(double)> lambda; // std::function<int(double)> lambda;
virtual ~Process(){} virtual ~TimeProcess(){}
virtual void schedule(uint64_t delay){ virtual void schedule(uint64_t delay){
wakeDelay = delay; wakeDelay = delay;
wakeEnable = true; wakeEnable = true;
@ -47,7 +47,16 @@ public:
}; };
class ClockDomain : public Process{ class SensitiveProcess{
public:
virtual ~SensitiveProcess(){}
virtual void tick(uint64_t time){
}
};
class ClockDomain : public TimeProcess{
public: public:
CData* clk; CData* clk;
CData* reset; CData* reset;
@ -91,7 +100,7 @@ public:
}; };
class AsyncReset : public Process{ class AsyncReset : public TimeProcess{
public: public:
CData* reset; CData* reset;
uint32_t state; uint32_t state;
@ -144,7 +153,7 @@ bool SetSocketBlockingEnabled(int fd, bool blocking)
#endif #endif
} }
class Jtag : public Process{ class Jtag : public TimeProcess{
public: public:
CData *tms, *tdi, *tdo, *tck; CData *tms, *tdi, *tdo, *tck;
enum State {reset}; enum State {reset};
@ -268,7 +277,8 @@ class success : public std::exception { };
class Workspace{ class Workspace{
public: public:
static uint32_t cycles; static uint32_t cycles;
vector<Process*> processes; vector<TimeProcess*> timeProcesses;
vector<SensitiveProcess*> checkProcesses;
VBriey* top; VBriey* top;
bool resetDone = false; bool resetDone = false;
double timeToSec = 1e-12; double timeToSec = 1e-12;
@ -294,7 +304,8 @@ public:
delete tfp; delete tfp;
#endif #endif
for(Process* p : processes) delete p; for(auto* p : timeProcesses) delete p;
for(auto* p : checkProcesses) delete p;
} }
@ -338,7 +349,7 @@ public:
try { try {
while(1){ while(1){
uint64_t delay = ~0l; uint64_t delay = ~0l;
for(Process* p : processes) for(TimeProcess* p : timeProcesses)
if(p->wakeEnable && p->wakeDelay < delay) if(p->wakeEnable && p->wakeDelay < delay)
delay = p->wakeDelay; delay = p->wakeDelay;
@ -348,7 +359,7 @@ public:
if(delay != 0){ if(delay != 0){
dump(time); dump(time);
} }
for(Process* p : processes) { for(TimeProcess* p : timeProcesses) {
p->wakeDelay -= delay; p->wakeDelay -= delay;
if(p->wakeDelay == 0){ if(p->wakeDelay == 0){
p->wakeEnable = false; p->wakeEnable = false;
@ -357,7 +368,7 @@ public:
} }
top->eval(); top->eval();
for(auto* p : checkProcesses) p->tick(time);
if(delay != 0){ if(delay != 0){
if(time - tickLastSimTime > 1000*400000 || time - tickLastSimTime > 1.0*speedFactor/timeToSec){ if(time - tickLastSimTime > 1000*400000 || time - tickLastSimTime > 1.0*speedFactor/timeToSec){
@ -366,7 +377,9 @@ public:
uint64_t diffInNanos = end_time.tv_sec*1e9 + end_time.tv_nsec - tick_time.tv_sec*1e9 - tick_time.tv_nsec; uint64_t diffInNanos = end_time.tv_sec*1e9 + end_time.tv_nsec - tick_time.tv_sec*1e9 - tick_time.tv_nsec;
tick_time = end_time; tick_time = end_time;
double dt = diffInNanos*1e-9; double dt = diffInNanos*1e-9;
#ifdef PRINT_PERF
printf("Simulation speed : %f ms/realTime\n",(time - tickLastSimTime)/dt*timeToSec*1e3); printf("Simulation speed : %f ms/realTime\n",(time - tickLastSimTime)/dt*timeToSec*1e3);
#endif
tickLastSimTime = time; tickLastSimTime = time;
} }
time += delay; time += delay;
@ -387,7 +400,7 @@ public:
if(flushCounter > 100000){ if(flushCounter > 100000){
#ifdef TRACE #ifdef TRACE
tfp->flush(); tfp->flush();
printf("flush\n"); //printf("flush\n");
#endif #endif
flushCounter = 0; flushCounter = 0;
} }
@ -620,6 +633,62 @@ public:
} }
}; };
class UartRx : public SensitiveProcess{
public:
CData *rx;
uint32_t uartTimeRate;
UartRx(CData *rx, uint32_t uartTimeRate){
this->rx = rx;
this->uartTimeRate = uartTimeRate;
}
enum State {START, DATA, STOP,START_SUCCESS};
State state = START;
uint64_t holdTime = 0;
CData holdValue;
char data;
uint32_t counter;
virtual void tick(uint64_t time){
if(time < holdTime){
if(*rx != holdValue){
cout << "UART RX FRAME ERROR" << endl;
holdTime = time;
state = START;
}
}else{
switch(state){
case START:
case START_SUCCESS:
if(state == START_SUCCESS){
cout << data << flush;
state = START;
}
if(*rx == 0 && time > uartTimeRate){
holdTime = time + uartTimeRate;
holdValue = *rx;
state = DATA;
counter = 0;
data = 0;
}
break;
case DATA:
data |= (*rx) << counter++;
if(counter == 8){
state = STOP;
}
holdValue = *rx;
holdTime = time + uartTimeRate;
break;
case STOP:
holdTime = time + uartTimeRate;
holdValue = 1;
state = START_SUCCESS;
break;
}
}
}
};
class BrieyWorkspace : public Workspace{ class BrieyWorkspace : public Workspace{
public: public:
@ -628,10 +697,12 @@ public:
ClockDomain *vgaClk = new ClockDomain(&top->io_vgaClk,NULL,40000,100000); ClockDomain *vgaClk = new ClockDomain(&top->io_vgaClk,NULL,40000,100000);
AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000); AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000);
Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,60000); Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,60000);
processes.push_back(axiClk); UartRx *uartRx = new UartRx(&top->io_uart_txd,(50000000/8/115200)*8*axiClk->tooglePeriod*2);
processes.push_back(vgaClk); timeProcesses.push_back(axiClk);
processes.push_back(asyncReset); timeProcesses.push_back(vgaClk);
processes.push_back(jtag); timeProcesses.push_back(asyncReset);
timeProcesses.push_back(jtag);
checkProcesses.push_back(uartRx);
SdramConfig *sdramConfig = new SdramConfig( SdramConfig *sdramConfig = new SdramConfig(
2, //byteCount 2, //byteCount

4
src/test/cpp/briey/makefile
View File

@ -1,5 +1,6 @@
DEBUG?=no DEBUG?=no
TRACE?=no TRACE?=no
PRINT_PERF?=no
TRACE_START=0 TRACE_START=0
ADDCFLAGS += -CFLAGS -pthread ADDCFLAGS += -CFLAGS -pthread
@ -13,6 +14,9 @@ endif
ifneq ($(DEBUG),yes) ifneq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS "-O3" ADDCFLAGS += -CFLAGS "-O3"
endif endif
ifeq ($(PRINT_PERF),yes)
ADDCFLAGS += -CFLAGS -DPRINT_PERF
endif
ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START} ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START}

60
src/test/cpp/briey/wip.gtkw Normal file
View File

@ -0,0 +1,60 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sat Jun 10 13:47:38 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd"
[dumpfile_mtime] "Sat Jun 10 13:46:48 2017"
[dumpfile_size] 485915260
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/wip.gtkw"
[timestart] 0
[size] 1776 953
[pos] -775 -353
*-18.000000 260000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.Briey.
[treeopen] TOP.Briey.axi_uartCtrl.
[sst_width] 269
[signals_width] 310
[sst_expanded] 1
[sst_vpaned_height] 503
@28
TOP.Briey.axi_uartCtrl.io_axiClk
@22
TOP.Briey.axi_uartCtrl.io_apb_PADDR[3:0]
@28
TOP.Briey.axi_uartCtrl.io_apb_PENABLE
@22
TOP.Briey.axi_uartCtrl.io_apb_PRDATA[31:0]
@28
TOP.Briey.axi_uartCtrl.io_apb_PREADY
TOP.Briey.axi_uartCtrl.io_apb_PSEL[0]
@22
TOP.Briey.axi_uartCtrl.io_apb_PWDATA[31:0]
@28
TOP.Briey.axi_uartCtrl.io_apb_PWRITE
@24
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_clockDivider[19:0]
@28
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_dataLength[2:0]
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_parity[1:0]
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_config_frame_stop[0]
TOP.Briey.axi_uartCtrl.uartCtrl_1.io_uart_txd
@22
TOP.Briey.axi_core_cpu.DebugPlugin_busReadDataReg[31:0]
@28
TOP.Briey.axi_core_cpu.DebugPlugin_firstCycle
TOP.Briey.axi_core_cpu.DebugPlugin_haltIt
TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak
TOP.Briey.axi_core_cpu.DebugPlugin_insertDecodeInstruction
TOP.Briey.axi_core_cpu.DebugPlugin_isPipActive
TOP.Briey.axi_core_cpu.DebugPlugin_isPipBusy
TOP.Briey.axi_core_cpu.DebugPlugin_resetIt
TOP.Briey.axi_core_cpu.DebugPlugin_stepIt
TOP.Briey.axi_core_cpu.decode_IS_EBREAK
TOP.Briey.axi_core_cpu.decode_arbitration_isValid
@22
TOP.Briey.axi_core_cpu.decode_PC[31:0]
@23
TOP.Briey.axi_core_cpu.decode_INSTRUCTION[31:0]
[pattern_trace] 1
[pattern_trace] 0