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VexRiscv
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Update verilator makefiles to support the last SpinalHDL changes (process merges)

This commit is contained in:
Dolu1990 2017-11-21 23:56:46 +01:00
parent 9b9bbaa4ad
commit b7f4f09814
5 changed files with 7 additions and 4 deletions
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3
src/main/scala/vexriscv/VexRiscv.scala
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@ -62,6 +62,9 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
writeBack.input(config.PC) keep() addAttribute(Verilator.public) writeBack.input(config.PC) keep() addAttribute(Verilator.public)
writeBack.arbitration.isValid keep() addAttribute(Verilator.public) writeBack.arbitration.isValid keep() addAttribute(Verilator.public)
writeBack.arbitration.isFiring keep() addAttribute(Verilator.public) writeBack.arbitration.isFiring keep() addAttribute(Verilator.public)
decode.arbitration.removeIt.noBackendCombMerge //Verilator perf
memory.arbitration.removeIt.noBackendCombMerge
execute.arbitration.flushAll.noBackendCombMerge
} }

2
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -326,7 +326,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
//Used to make the pipeline empty softly (for interrupts) //Used to make the pipeline empty softly (for interrupts)
val pipelineLiberator = new Area{ val pipelineLiberator = new Area{
val enable = False val enable = False.noBackendCombMerge //Verilator Perf
prefetch.arbitration.haltByOther setWhen(enable) prefetch.arbitration.haltByOther setWhen(enable)
val done = ! List(fetch, decode, execute, memory).map(_.arbitration.isValid).orR val done = ! List(fetch, decode, execute, memory).map(_.arbitration.isValid).orR
} }

2
src/test/cpp/briey/makefile
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@ -46,7 +46,7 @@ run: compile
./obj_dir/VBriey ./obj_dir/VBriey
verilate: verilate:
verilator -cc ../../../../Briey.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp verilator -cc ../../../../Briey.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
compile: verilate compile: verilate
make -j -C obj_dir/ -f VBriey.mk VBriey make -j -C obj_dir/ -f VBriey.mk VBriey

2
src/test/cpp/murax/makefile
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@ -29,7 +29,7 @@ run: compile
./obj_dir/VMurax ./obj_dir/VMurax
verilate: verilate:
verilator -cc ../../../../Murax.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp verilator -cc ../../../../Murax.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
compile: verilate compile: verilate
make -j -C obj_dir/ -f VMurax.mk VMurax make -j -C obj_dir/ -f VMurax.mk VMurax

2
src/test/cpp/regression/makefile
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@ -94,7 +94,7 @@ run: compile
./obj_dir/VVexRiscv ./obj_dir/VVexRiscv
verilate: verilate:
verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
compile: verilate compile: verilate
make -j -C obj_dir/ -f VVexRiscv.mk VVexRiscv make -j -C obj_dir/ -f VVexRiscv.mk VVexRiscv