Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

syncronize golden model with dut for lrsc reservation

Browse source
This commit is contained in:
Dolu1990 2022-01-10 19:55:28 +01:00
parent 6e77f32087
commit b8e904e43f
4 changed files with 12 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/main/scala/vexriscv/ip/DataCache.scala
View file

@ -175,6 +175,7 @@ case class FenceFlags() extends Bundle {
case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMasterSlave{ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMasterSlave{
val isValid = Bool() val isValid = Bool()
val isStuck = Bool() val isStuck = Bool()
val isFiring = Bool()
val isUser = Bool() val isUser = Bool()
val haltIt = Bool() val haltIt = Bool()
val isWrite = Bool() val isWrite = Bool()
@ -187,7 +188,7 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
val exclusiveOk = Bool() val exclusiveOk = Bool()
override def asMaster(): Unit = { override def asMaster(): Unit = {
out(isValid,isStuck,isUser, address, fence, storeData) out(isValid,isStuck,isUser, address, fence, storeData, isFiring)
in(haltIt, data, mmuException, unalignedAccess, accessError, isWrite, keepMemRspData, exclusiveOk) in(haltIt, data, mmuException, unalignedAccess, accessError, isWrite, keepMemRspData, exclusiveOk)
} }
} }
@ -864,7 +865,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
val lrSc = withInternalLrSc generate new Area{ val lrSc = withInternalLrSc generate new Area{
val reserved = RegInit(False) val reserved = RegInit(False)
when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck){ when(io.cpu.writeBack.isValid && io.cpu.writeBack.isFiring){
reserved setWhen(request.isLrsc) reserved setWhen(request.isLrsc)
reserved clearWhen(request.wr) reserved clearWhen(request.wr)
} }

1
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View file

@ -395,6 +395,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
import managementStage._ import managementStage._
cache.io.cpu.writeBack.isValid := arbitration.isValid && input(MEMORY_ENABLE) cache.io.cpu.writeBack.isValid := arbitration.isValid && input(MEMORY_ENABLE)
cache.io.cpu.writeBack.isStuck := arbitration.isStuck cache.io.cpu.writeBack.isStuck := arbitration.isStuck
cache.io.cpu.writeBack.isFiring := arbitration.isFiring
cache.io.cpu.writeBack.isUser := (if(privilegeService != null) privilegeService.isUser() else False) cache.io.cpu.writeBack.isUser := (if(privilegeService != null) privilegeService.isUser() else False)
cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA)) cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA))
cache.io.cpu.writeBack.storeData.subdivideIn(32 bits).foreach(_ := input(MEMORY_STORE_DATA_RF)) cache.io.cpu.writeBack.storeData.subdivideIn(32 bits).foreach(_ := input(MEMORY_STORE_DATA_RF))

5
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View file

@ -462,8 +462,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
val atomic = withLrSc generate new Area{ val atomic = withLrSc generate new Area{
val reserved = RegInit(False) val reserved = RegInit(False)
insert(ATOMIC_HIT) := reserved insert(ATOMIC_HIT) := reserved
when(arbitration.isFiring && input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){ when(arbitration.isFiring && input(MEMORY_ENABLE) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){
reserved := !input(MEMORY_STORE) reserved setWhen(input(MEMORY_ATOMIC))
reserved clearWhen(input(MEMORY_STORE))
} }
when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){ when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){
skipCmd := True skipCmd := True

5
src/test/cpp/regression/main.cpp
View file

@ -1111,6 +1111,7 @@ public:
lrscReserved = false; lrscReserved = false;
uint32_t pAddr; uint32_t pAddr;
if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; } if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; }
if(dRead(pAddr, 4, (uint8_t*)&readValue)){ if(dRead(pAddr, 4, (uint8_t*)&readValue)){
@ -1178,6 +1179,7 @@ public:
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
dWrite(pAddr, 4, (uint8_t*)&i16_rf2); dWrite(pAddr, 4, (uint8_t*)&i16_rf2);
pcWrite(pc + 2); pcWrite(pc + 2);
lrscReserved = false;
} }
}break; }break;
case 8: rfWrite(rd32, regs[rd32] + i16_imm); pcWrite(pc + 2); break; case 8: rfWrite(rd32, regs[rd32] + i16_imm); pcWrite(pc + 2); break;
@ -1243,6 +1245,7 @@ public:
} else { } else {
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
dWrite(pAddr, 4, (uint8_t*)&regs[iBits(2,5)]); pcWrite(pc + 2); dWrite(pAddr, 4, (uint8_t*)&regs[iBits(2,5)]); pcWrite(pc + 2);
lrscReserved = false;
} }
}break; }break;
} }
@ -2610,7 +2613,6 @@ public:
bool hit = reservationValid && reservationAddress == top->dBus_cmd_payload_address; bool hit = reservationValid && reservationAddress == top->dBus_cmd_payload_address;
rsp.exclusive = hit; rsp.exclusive = hit;
cancel = !hit; cancel = !hit;
reservationValid = false;
} }
if(!cancel) { if(!cancel) {
for(int idx = 0;idx < 1;idx++){ for(int idx = 0;idx < 1;idx++){
@ -2621,6 +2623,7 @@ public:
} }
} }
reservationValid = false;
rsp.last = true; rsp.last = true;
rsp.error = error; rsp.error = error;
rsps.push(rsp); rsps.push(rsp);