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VexRiscv
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This commit is contained in:
Charles Papon 2017-06-15 13:54:34 +02:00
parent 88a2c4a603
commit bc90331c49
2 changed files with 3 additions and 7 deletions
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6
README.md
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@ -25,13 +25,13 @@ You can find two example of CPU instantiation in :
- src/main/scala/VexRiscv/GenFull.scala - src/main/scala/VexRiscv/GenFull.scala
- src/main/scala/VexRiscv/GenSmallest.scala - src/main/scala/VexRiscv/GenSmallest.scala
To generate the corresponding RTL as a VexRiscv.v file, run : To generate the corresponding RTL as a VexRiscv.v file, run (it could take time the first time you run it):
```sh ```sh
sbt run-main VexRiscv.GenFull sbt "run-main VexRiscv.GenFull"
# or # or
sbt run-main VexRiscv.GenSmallest sbt "run-main VexRiscv.GenSmallest"
``` ```
## Tests ## Tests

4
src/main/scala/VexRiscv/demo/Briey.scala
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@ -117,10 +117,6 @@ class Briey(config: BrieyConfig) extends Component{
reset = resetCtrl.vgaReset reset = resetCtrl.vgaReset
) )
val jtagClockDomain = ClockDomain(
clock = io.jtag.tck
)
val axi = new ClockingArea(axiClockDomain) { val axi = new ClockingArea(axiClockDomain) {
val ram = Axi4SharedOnChipRam( val ram = Axi4SharedOnChipRam(
dataWidth = 32, dataWidth = 32,