Merge remote-tracking branch 'origin/spinalhdl_reworkDev'

build.sbt

@@ -9,7 +9,7 @@ scalaVersion := "2.11.8"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.10.15",
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.11.0",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.10.15",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.11.0",
   "org.yaml" % "snakeyaml" % "1.8"
-)
+)

src/main/scala/vexriscv/Stage.scala

@@ -12,13 +12,12 @@ class Stageable[T <: Data](val dataType : T) extends HardType[T](dataType) with
 
 class Stage() extends Area{
   def outsideCondScope[T](that : => T) : T = {
-    val condStack = GlobalData.get.conditionalAssignStack.stack.toList
+    val body = Component.current.dslBody
-    val switchStack = GlobalData.get.switchStack.stack.toList
+    body.push()
-    GlobalData.get.conditionalAssignStack.stack.clear()
+    val swapContext = body.swap()
-    GlobalData.get.switchStack.stack.clear()
     val ret = that
-    GlobalData.get.conditionalAssignStack.stack.pushAll(condStack.reverseIterator)
+    body.pop()
-    GlobalData.get.switchStack.stack.pushAll(switchStack.reverseIterator)
+    swapContext.appendBack()
     ret
   }
 

src/main/scala/vexriscv/TestsWorkspace.scala

@@ -28,7 +28,7 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
 
 object TestsWorkspace {
   def main(args: Array[String]) {
-    SpinalVerilog {
+    SpinalConfig(mergeAsyncProcess = false).generateVerilog {
       val configFull = VexRiscvConfig(
         plugins = List(
           new PcManagerSimplePlugin(

src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala

@@ -54,5 +54,5 @@ object GenSmallestNoCsr extends App{
       )
     )
   )
-  SpinalVerilog(cpu())
+  SpinalConfig(mergeAsyncProcess = false).generateVerilog(cpu())
 }

src/main/scala/vexriscv/plugin/BranchPlugin.scala

@@ -147,8 +147,8 @@ class BranchPlugin(earlyBranch : Boolean,
     import pipeline._
     import pipeline.config._
 
-    val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache")
+    val historyCache = if(prediction == DYNAMIC) Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache") else null
-    val historyCacheWrite = historyCache.writePort
+    val historyCacheWrite = if(prediction == DYNAMIC) historyCache.writePort else null
 
     //Read historyCache
     if(prediction == DYNAMIC) fetch plug new Area{

src/main/scala/vexriscv/plugin/CsrPlugin.scala

@@ -260,10 +260,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
 
       //Define CSR registers
       val misa = new Area{
-        val base = Reg(UInt(2 bits)) init(U"01")
+        val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch
-        val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit)
+        val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch
       }
-      val mtvec = RegInit(U(mtvecInit,xlen bits))
+      val mtvec = RegInit(U(mtvecInit,xlen bits)) allowUnsetRegToAvoidLatch
       val mepc = Reg(UInt(xlen bits))
       val mstatus = new Area{
         val MIE, MPIE = RegInit(False)
@@ -337,7 +337,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
       val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
         val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
         val exceptionValids = Vec(Bool,stages.length)
-        val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length)
+        val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).allowUnsetRegToAvoidLatch
         val exceptionContext = Reg(ExceptionCause())
         val pipelineHasException = exceptionValids.orR   //TODO FMAX maybe could be partialy pipelined
 

src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala

@@ -2,6 +2,7 @@ package vexriscv.plugin
 
 import vexriscv._
 import spinal.core._
+import spinal.core.internals.Literal
 import spinal.lib._
 
 import scala.collection.mutable
@@ -83,11 +84,11 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
     stageables.foreach(e => {
       defaults.get(e) match {
         case Some(value) => {
-          value.input match {
+          value.head.source match {
             case literal: EnumLiteral[_] => literal.fixEncoding(e.dataType.asInstanceOf[SpinalEnumCraft[_]].getEncoding)
             case _ =>
           }
-          defaultValue += value.input.asInstanceOf[Literal].getValue << offset
+          defaultValue += value.head.source .asInstanceOf[Literal].getValue << offset
           defaultCare += ((BigInt(1) << e.dataType.getBitsWidth) - 1) << offset
 
         }
@@ -102,12 +103,12 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
       var decodedValue = defaultValue
       var decodedCare = defaultCare
       for((e, literal) <- values){
-        literal.input match{
+        literal.head.source  match{
           case literal : EnumLiteral[_] => literal.fixEncoding(e.dataType.asInstanceOf[SpinalEnumCraft[_]].getEncoding)
           case _ =>
         }
         val offset = offsetOf(e)
-        decodedValue |= literal.input.asInstanceOf[Literal].getValue << offset
+        decodedValue |= literal.head.source.asInstanceOf[Literal].getValue << offset
         decodedCare  |= ((BigInt(1) << e.dataType.getBitsWidth)-1) << offset
       }
       (Masked(key.value,key.careAbout),Masked(decodedValue,decodedCare))
@@ -145,7 +146,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
       val stageables = encodings.flatMap(_._2.map(_._1)).toSet
       stageables.foreach(e => out(RegNext(RegNext(toplevel.decode.insert(e)).setName(e.getName()))))
       if(catchIllegalInstruction) out(RegNext(RegNext(toplevel.decode.insert(LEGAL_INSTRUCTION)).setName(LEGAL_INSTRUCTION.getName())))
-      toplevel.getAdditionalNodesRoot.clear()
+    //  toplevel.getAdditionalNodesRoot.clear()
     }
   }
 }