Hardware/VexRiscv
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Merge remote-tracking branch 'origin/spinalhdl_reworkDev'

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This commit is contained in:
Dolu1990 2017-11-12 13:08:05 +01:00
commit be3d301eaf
7 changed files with 22 additions and 22 deletions
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6
build.sbt
View file

@ -9,7 +9,7 @@ scalaVersion := "2.11.8"
EclipseKeys.withSource := true
libraryDependencies ++= Seq(
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.10.15",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.10.15",
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.11.0",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.11.0",
"org.yaml" % "snakeyaml" % "1.8"
)
)

11
src/main/scala/vexriscv/Stage.scala
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@ -12,13 +12,12 @@ class Stageable[T <: Data](val dataType : T) extends HardType[T](dataType) with
class Stage() extends Area{
def outsideCondScope[T](that : => T) : T = {
val condStack = GlobalData.get.conditionalAssignStack.stack.toList
val switchStack = GlobalData.get.switchStack.stack.toList
GlobalData.get.conditionalAssignStack.stack.clear()
GlobalData.get.switchStack.stack.clear()
val body = Component.current.dslBody
body.push()
val swapContext = body.swap()
val ret = that
GlobalData.get.conditionalAssignStack.stack.pushAll(condStack.reverseIterator)
GlobalData.get.switchStack.stack.pushAll(switchStack.reverseIterator)
body.pop()
swapContext.appendBack()
ret
}

2
src/main/scala/vexriscv/TestsWorkspace.scala
View file

@ -28,7 +28,7 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
object TestsWorkspace {
def main(args: Array[String]) {
SpinalVerilog {
SpinalConfig(mergeAsyncProcess = false).generateVerilog {
val configFull = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(

2
src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala
View file

@ -54,5 +54,5 @@ object GenSmallestNoCsr extends App{
)
)
)
SpinalVerilog(cpu())
SpinalConfig(mergeAsyncProcess = false).generateVerilog(cpu())
}

4
src/main/scala/vexriscv/plugin/BranchPlugin.scala
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@ -147,8 +147,8 @@ class BranchPlugin(earlyBranch : Boolean,
import pipeline._
import pipeline.config._
val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache")
val historyCacheWrite = historyCache.writePort
val historyCache = if(prediction == DYNAMIC) Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache") else null
val historyCacheWrite = if(prediction == DYNAMIC) historyCache.writePort else null
//Read historyCache
if(prediction == DYNAMIC) fetch plug new Area{

8
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -260,10 +260,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
//Define CSR registers
val misa = new Area{
val base = Reg(UInt(2 bits)) init(U"01")
val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit)
val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch
val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch
}
val mtvec = RegInit(U(mtvecInit,xlen bits))
val mtvec = RegInit(U(mtvecInit,xlen bits)) allowUnsetRegToAvoidLatch
val mepc = Reg(UInt(xlen bits))
val mstatus = new Area{
val MIE, MPIE = RegInit(False)
@ -337,7 +337,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
val exceptionValids = Vec(Bool,stages.length)
val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length)
val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).allowUnsetRegToAvoidLatch
val exceptionContext = Reg(ExceptionCause())
val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined

11
src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
View file

@ -2,6 +2,7 @@ package vexriscv.plugin
import vexriscv._
import spinal.core._
import spinal.core.internals.Literal
import spinal.lib._
import scala.collection.mutable
@ -83,11 +84,11 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
stageables.foreach(e => {
defaults.get(e) match {
case Some(value) => {
value.input match {
value.head.source match {
case literal: EnumLiteral[_] => literal.fixEncoding(e.dataType.asInstanceOf[SpinalEnumCraft[_]].getEncoding)
case _ =>
}
defaultValue += value.input.asInstanceOf[Literal].getValue << offset
defaultValue += value.head.source .asInstanceOf[Literal].getValue << offset
defaultCare += ((BigInt(1) << e.dataType.getBitsWidth) - 1) << offset
}
@ -102,12 +103,12 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
var decodedValue = defaultValue
var decodedCare = defaultCare
for((e, literal) <- values){
literal.input match{
literal.head.source match{
case literal : EnumLiteral[_] => literal.fixEncoding(e.dataType.asInstanceOf[SpinalEnumCraft[_]].getEncoding)
case _ =>
}
val offset = offsetOf(e)
decodedValue |= literal.input.asInstanceOf[Literal].getValue << offset
decodedValue |= literal.head.source.asInstanceOf[Literal].getValue << offset
decodedCare |= ((BigInt(1) << e.dataType.getBitsWidth)-1) << offset
}
(Masked(key.value,key.careAbout),Masked(decodedValue,decodedCare))
@ -145,7 +146,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
val stageables = encodings.flatMap(_._2.map(_._1)).toSet
stageables.foreach(e => out(RegNext(RegNext(toplevel.decode.insert(e)).setName(e.getName()))))
if(catchIllegalInstruction) out(RegNext(RegNext(toplevel.decode.insert(LEGAL_INSTRUCTION)).setName(LEGAL_INSTRUCTION.getName())))
toplevel.getAdditionalNodesRoot.clear()
// toplevel.getAdditionalNodesRoot.clear()
}
}
}