Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update README.md

This commit is contained in:
Dolu1990 2017-05-19 17:13:33 +02:00 committed by GitHub
parent a5364ad001
commit cabf602efc
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -6,6 +6,8 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som
- 1.17 DMIPS/Mhz with all extension - 1.17 DMIPS/Mhz with all extension
- Optimized for FPGA - Optimized for FPGA
- Optional MUL/DIV/REM extension - Optional MUL/DIV/REM extension
- Optional instruction and data caches
- Optional MMU
- Two implementation of shift instructions, Single cycle / shiftNumber cycle - Two implementation of shift instructions, Single cycle / shiftNumber cycle
- Each stage could have bypass or interlock hazard logic - Each stage could have bypass or interlock hazard logic
- FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV - FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV