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Add MuraxAsicBlackBox example

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Dolu1990 2021-03-04 10:16:45 +01:00
parent 4bdab667cc
commit caf1bde49b
1 changed files with 10 additions and 0 deletions
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10
src/main/scala/vexriscv/demo/Murax.scala
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@ -483,3 +483,13 @@ object Murax_arty{
SpinalVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB, onChipRamHexFile = hex))) SpinalVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB, onChipRamHexFile = hex)))
} }
} }
object MuraxAsicBlackBox{
def main(args: Array[String]) {
println("Warning this soc do not has any rom to boot on.")
val config = SpinalConfig()
config.addStandardMemBlackboxing(blackboxAll)
config.generateVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB)))
}
}