#240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust

src/main/scala/vexriscv/plugin/CsrPlugin.scala

@@ -532,6 +532,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
   override def setup(pipeline: VexRiscv): Unit = {
     import pipeline.config._
 
+    if(!config.ebreakGen) {
+      SpinalWarning("This VexRiscv configuration is set without software ebreak instruction support. Some software may rely on it (ex: Rust). (This isn't related to JTAG ebreak)")
+    }
+
     csrMapping = new CsrMapping()
 
     inWfi = False.addTag(Verilator.public)

src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala

@@ -79,6 +79,9 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false,
 
 
   override def setup(pipeline: VexRiscv): Unit = {
+    if(!catchIllegalInstruction) {
+      SpinalWarning("This VexRiscv configuration is set without illegal instruction catch support. Some software may rely on it (ex: Rust)")
+    }
     if(catchIllegalInstruction) {
       val exceptionService = pipeline.plugins.filter(_.isInstanceOf[ExceptionService]).head.asInstanceOf[ExceptionService]
       decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode).setName("decodeExceptionPort")