Add EmbeddedRiscvJtag.debugCd
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@ -152,6 +152,7 @@ object TestsWorkspace {
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version = 1,
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idle = 7
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),
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debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
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withTunneling = false,
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withTap = true
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)
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@ -82,6 +82,7 @@ object GenFullWithRiscvPrivilegedDebugJtag extends App{
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version = 1,
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idle = 7
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),
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debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
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withTap = true,
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withTunneling = false
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),
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@ -483,6 +483,7 @@ object VexRiscvCustomSynthesisBench {
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version = 1,
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idle = 7
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),
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debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
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withTunneling = false,
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withTap = true
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)).setDefinitionName(getRtlPath().split("\\.").head))
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@ -13,6 +13,7 @@ import vexriscv._
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class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
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var debugCd : ClockDomain = null,
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var withTap : Boolean = true,
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var withTunneling : Boolean = false
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) extends Plugin[VexRiscv] with VexRiscvRegressionArg{
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@ -24,16 +25,17 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
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var jtagInstruction : JtagTapInstructionCtrl = null
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var ndmreset : Bool = null
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// val debugCd = Handle[ClockDomain].setName("debugCd")
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// val noTapCd = Handle[ClockDomain].setName("jtagCd")
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def setDebugCd(cd : ClockDomain) : this.type = {debugCd = cd; this}
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override def setup(pipeline: VexRiscv): Unit = {
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jtag = withTap generate slave(Jtag()).setName("jtag")
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jtagInstruction = !withTap generate slave(JtagTapInstructionCtrl()).setName("jtagInstruction")
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ndmreset = out(Bool()).setName("ndmreset")
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assert(debugCd != null, "You need to set the debugCd of the VexRiscv EmbeddedRiscvJtag.")
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}
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override def build(pipeline: VexRiscv): Unit = {
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override def build(pipeline: VexRiscv): Unit = debugCd{
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val XLEN = 32
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val dm = DebugModule(
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DebugModuleParameter(
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@ -3150,6 +3150,7 @@ void Workspace::fillSimELements(){
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#endif
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#ifdef RISCV_JTAG
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simElements.push_back(new Jtag(&top->jtag_tms, &top->jtag_tdi, &top->jtag_tdo, &top->jtag_tck, 4));
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simElements.push_back(new VexRiscvJtag(this));
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#endif
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#ifdef VEXRISCV_JTAG
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simElements.push_back(new Jtag(&top->jtag_tms, &top->jtag_tdi, &top->jtag_tdo, &top->jtag_tck, 4));
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