Add EmbeddedRiscvJtag.debugCd

src/main/scala/vexriscv/TestsWorkspace.scala

@@ -152,6 +152,7 @@ object TestsWorkspace {
           version      = 1,
           idle         = 7
         ),
+        debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
         withTunneling = false,
         withTap = true
       )

src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala

@@ -82,6 +82,7 @@ object GenFullWithRiscvPrivilegedDebugJtag extends App{
           version      = 1,
           idle         = 7
         ),
+        debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
         withTap = true,
         withTunneling = false
       ),

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -483,6 +483,7 @@ object VexRiscvCustomSynthesisBench {
           version      = 1,
           idle         = 7
         ),
+        debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
         withTunneling = false,
         withTap = true
       )).setDefinitionName(getRtlPath().split("\\.").head))

src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala

@@ -13,6 +13,7 @@ import vexriscv._
 
 
 class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
+                        var debugCd : ClockDomain = null,
                         var withTap : Boolean = true,
                         var withTunneling : Boolean = false
                         ) extends Plugin[VexRiscv] with VexRiscvRegressionArg{
@@ -24,16 +25,17 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
   var jtagInstruction : JtagTapInstructionCtrl = null
   var ndmreset : Bool = null
 
-//  val debugCd = Handle[ClockDomain].setName("debugCd")
+
-//  val noTapCd = Handle[ClockDomain].setName("jtagCd")
+  def setDebugCd(cd : ClockDomain) : this.type = {debugCd = cd; this}
 
   override def setup(pipeline: VexRiscv): Unit = {
     jtag = withTap generate slave(Jtag()).setName("jtag")
     jtagInstruction = !withTap generate slave(JtagTapInstructionCtrl()).setName("jtagInstruction")
     ndmreset = out(Bool()).setName("ndmreset")
+    assert(debugCd != null, "You need to set the debugCd of the VexRiscv EmbeddedRiscvJtag.")
   }
 
-  override def build(pipeline: VexRiscv): Unit = {
+  override def build(pipeline: VexRiscv): Unit = debugCd{
     val XLEN = 32
     val dm = DebugModule(
       DebugModuleParameter(

src/test/cpp/regression/main.cpp

@@ -3150,6 +3150,7 @@ void Workspace::fillSimELements(){
 	#endif
 	#ifdef RISCV_JTAG
 		simElements.push_back(new Jtag(&top->jtag_tms, &top->jtag_tdi, &top->jtag_tdo, &top->jtag_tck, 4));
+        simElements.push_back(new VexRiscvJtag(this));
 	#endif
     #ifdef VEXRISCV_JTAG
         simElements.push_back(new Jtag(&top->jtag_tms, &top->jtag_tdi, &top->jtag_tdo, &top->jtag_tck, 4));