This commit is contained in:
Dolu1990 2017-03-12 12:39:33 +01:00
parent cb1b73bc2b
commit ec4837a744
3 changed files with 49 additions and 1 deletions

4
sim/cmd.txt Normal file
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@ -0,0 +1,4 @@
verilator -cc ../VexRiscv.v --trace -Wno-WIDTH --exe tester.cpp
make -j -C obj_dir/ -f VVexRiscv.mk VVexRiscv

38
sim/tester.cpp Normal file
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@ -0,0 +1,38 @@
#include "VVexRiscv.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
int main(int argc, char **argv, char **env) {
int i;
int clk;
Verilated::commandArgs(argc, argv);
// init top verilog instance
VVexRiscv* top = new VVexRiscv;
// init trace dump
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("sim.vcd");
// initialize simulation inputs
top->clk = 1;
// top->rst = 1;
// top->cen = 0;
// top->wen = 0;
// top->dat = 0x55;
// run simulation for 100 clock periods
for (i=0; i<20; i++) {
// top->rst = (i < 2);
// dump variables into VCD file and toggle clock
for (clk=0; clk<2; clk++) {
tfp->dump (2*i+clk);
top->clk = !top->clk;
top->eval ();
}
// top->cen = (i > 5);
// top->wen = (i == 10);
if (Verilated::gotFinish()) exit(0);
}
tfp->close();
exit(0);
}

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@ -275,6 +275,12 @@ class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
BranchCtrlEnum.JALR -> (input(REG1).asUInt + imm.i_sext.asUInt),
default -> (input(PC) + imm.b_sext.asUInt) //B
)
when(jumpInterface.valid){
prefetch.arbitration.removeIt := True
fetch.arbitration.removeIt := True
decode.arbitration.removeIt := True
}
}
}
}
@ -809,7 +815,7 @@ class OutputAluResult extends Plugin[VexRiscv]{
object TopLevel {
def main(args: Array[String]) {
SpinalVhdl{
SpinalVerilog{
val config = VexRiscvConfig(
pcWidth = 32
)