wip
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@ -0,0 +1,4 @@
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verilator -cc ../VexRiscv.v --trace -Wno-WIDTH --exe tester.cpp
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make -j -C obj_dir/ -f VVexRiscv.mk VVexRiscv
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#include "VVexRiscv.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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int main(int argc, char **argv, char **env) {
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int i;
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int clk;
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Verilated::commandArgs(argc, argv);
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// init top verilog instance
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VVexRiscv* top = new VVexRiscv;
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// init trace dump
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Verilated::traceEverOn(true);
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VerilatedVcdC* tfp = new VerilatedVcdC;
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top->trace (tfp, 99);
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tfp->open ("sim.vcd");
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// initialize simulation inputs
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top->clk = 1;
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// top->rst = 1;
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// top->cen = 0;
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// top->wen = 0;
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// top->dat = 0x55;
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// run simulation for 100 clock periods
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for (i=0; i<20; i++) {
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// top->rst = (i < 2);
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// dump variables into VCD file and toggle clock
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for (clk=0; clk<2; clk++) {
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tfp->dump (2*i+clk);
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top->clk = !top->clk;
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top->eval ();
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}
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// top->cen = (i > 5);
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// top->wen = (i == 10);
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if (Verilated::gotFinish()) exit(0);
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}
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tfp->close();
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exit(0);
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}
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@ -275,6 +275,12 @@ class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
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BranchCtrlEnum.JALR -> (input(REG1).asUInt + imm.i_sext.asUInt),
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default -> (input(PC) + imm.b_sext.asUInt) //B
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)
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when(jumpInterface.valid){
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prefetch.arbitration.removeIt := True
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fetch.arbitration.removeIt := True
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decode.arbitration.removeIt := True
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}
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}
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}
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}
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@ -809,7 +815,7 @@ class OutputAluResult extends Plugin[VexRiscv]{
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object TopLevel {
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def main(args: Array[String]) {
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SpinalVhdl{
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SpinalVerilog{
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val config = VexRiscvConfig(
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pcWidth = 32
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)
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